Справочник Пользователя для HP (Hewlett-Packard) 441877-00F
Diagnostics 53
For CX4 (copper interface) applications an external module is required to connect the four transmit lanes
to the four corresponding receive lanes. This module must contain all of the associated handshake signals
required to redirect the four transmit lanes to the four receive lanes.
For XFP (10 Gigabit small form factor pluggable module) applications, an 850 nm multi-mode cable with
required to redirect the four transmit lanes to the four receive lanes.
For XFP (10 Gigabit small form factor pluggable module) applications, an 850 nm multi-mode cable with
LC connectors is required to connect the transmit lane to the receive lane externally.
Link. Reports the status of the link as up or down.
LED. Interactive test that causes the LEDs to blink. The software/driver has no auto-detect mechanism for
Link. Reports the status of the link as up or down.
LED. Interactive test that causes the LEDs to blink. The software/driver has no auto-detect mechanism for
checking LEDs. Visually inspect the LEDs on the adapter. The LEDs should blink for several seconds. No
blinking LEDs indicates that the test failed.
All Tests. Runs all of the diagnostic tests described in this section by using the single command.
All Tests. Runs all of the diagnostic tests described in this section by using the single command.
HP NC-Series Broadcom Multifunction adapter
diagnostics
diagnostics
1.
Boot to DOS or the EFI shell.
2.
From the DOS prompt navigate to the \APPS\DIAGS\MFDIAG directory.
3.
Type
XDIAG
and press the Enter key. The diagnostic tests run automatically.
About the XDIAG.exe diagnostic tests
The xdiag.exe diagnostic tests are divided into four groups: Group A: Register tests; Group B: Memory
The xdiag.exe diagnostic tests are divided into four groups: Group A: Register tests; Group B: Memory
tests; Group C: Block tests; an Group D: Miscellaneous tests.
Group A: Register tests
Group A: Register tests
•
A1. Register test
This tests the chip registers, accessible through PCI/PCI-E bus, for their read-only and read/write
attributes. Some critical registers are not tested as the system and/or the chip becomes unstable
when the values change.
This tests the chip registers, accessible through PCI/PCI-E bus, for their read-only and read/write
attributes. Some critical registers are not tested as the system and/or the chip becomes unstable
when the values change.
•
A2. PCI configuration test
This test checks the functionality of the BAR size configuration by examining the BAR value as the
This test checks the functionality of the BAR size configuration by examining the BAR value as the
BAR size varies.
•
A3. Interrupt test
This test checks to see if the system (OS) receives the interrupt artificially generated by the chip and if
the software ISR is properly invoked.
This test checks to see if the system (OS) receives the interrupt artificially generated by the chip and if
the software ISR is properly invoked.
•
A4.
Not used
Not used
•
A5. MSI test
This test checks for the correct behavior of the MSI, making sure no interrupt is generated other than
the message. It also runs the negative test to make sure no message is generated when interrupt is
This test checks for the correct behavior of the MSI, making sure no interrupt is generated other than
the message. It also runs the negative test to make sure no message is generated when interrupt is
masked off.
•
A6. Memory BIST
This tests all memory modules inside the chip using Built-In-Self-Test (BIST).
This tests all memory modules inside the chip using Built-In-Self-Test (BIST).
•
A7. Network link test