Справочник Пользователя для HP (Hewlett-Packard) 441877-00F
Diagnostics 56
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D6. RPC test (D06)
This test checks the receive catch-up path by sending packets to a different Tx chain. The packets will
go through the RPC logic and return to the receive buffers as Rx packets. The integrity of each packet
This test checks the receive catch-up path by sending packets to a different Tx chain. The packets will
go through the RPC logic and return to the receive buffers as Rx packets. The integrity of each packet
is checked to ensure no data corruption.
HP NC-Series Broadcom adapter diagnostics
Starting the Q57DIAG.exe tests
1.
Boot to DOS or the EFI shell.
2.
From the DOS prompt or shell navigate to the \APPS\DIAGS\Q57 directory.
3.
Type
Q57DIAG.
exe and press the Enter key. The diagnostic tests run automatically.
Test descriptions
The tests are divided into four groups: Register tests, Memory tests, Miscellaneous tests, and Data tests.
The tests are divided into four groups: Register tests, Memory tests, Miscellaneous tests, and Data tests.
They are identified as group A, B, C, and D.
Group A: Register tests
Group A: Register tests
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A1. Indirect register test
Using indirect addressing method, this test writes increment data into the MAC Hash Register table
and reads back for verification. The memory read/write is done 100 times while incrementing test
Using indirect addressing method, this test writes increment data into the MAC Hash Register table
and reads back for verification. The memory read/write is done 100 times while incrementing test
data.
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A2. Control register test
Each register specified in the configuration contents are defined as read only bit and read/write bit.
The test writes zero and one into the test bits to ensure the read only bits are not changed and
read/write bits are changed accordingly.
Each register specified in the configuration contents are defined as read only bit and read/write bit.
The test writes zero and one into the test bits to ensure the read only bits are not changed and
read/write bits are changed accordingly.
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A3. Interrupt test
This test verifies the interrupt functionality. It enables interrupt and then waits for the interrupt to
This test verifies the interrupt functionality. It enables interrupt and then waits for the interrupt to
occur. It waits for 500ms and reports an error if it could not generate interrupts.
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A4. Built-In-Self test
This test initiates Hardware Built-In-Self-Test (BIST) and then waits for the test result returned by
hardware. The hardware could not generate interrupts.
This test initiates Hardware Built-In-Self-Test (BIST) and then waits for the test result returned by
hardware. The hardware could not generate interrupts.
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A5. PCI Cfg register test
This test verifies the access integrity of the PCI config registers.
This test verifies the access integrity of the PCI config registers.
Group B: Memory tests
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B1. Scratch pad test
This tests the scratch pad SRAM on board. The following tests are performed:
This tests the scratch pad SRAM on board. The following tests are performed:
o
Address test: Writes each address with unique increment data. Reads back data to ensure data
is correct. After filling the entire data with the unique data, the program reads back data again
is correct. After filling the entire data with the unique data, the program reads back data again
to ensure data stays the same.
o
Walking one bit test: For each address, data one is written and read back for testing. Then the
data is shifted left one bit, so the data becomes two and the same test is run again. It repeats for
32 times until the test bit is shifted out of test data. The same test is repeated for the entire test
data is shifted left one bit, so the data becomes two and the same test is run again. It repeats for
32 times until the test bit is shifted out of test data. The same test is repeated for the entire test
range.