Справочник Пользователя для HGST TRAVELSTAR 80GN 30GB ATA5 08K0910
Модели
08K0910
6.4.1 Physical dimensions and weight ...................................................................................31
6.4.2 Mounting hole locations ...............................................................................................32
6.4.3 Connector and jumper description ................................................................................32
6.4.4 Mounting orientation ....................................................................................................33
6.4.5 Load/unload mechanism ...............................................................................................33
6.4.2 Mounting hole locations ...............................................................................................32
6.4.3 Connector and jumper description ................................................................................32
6.4.4 Mounting orientation ....................................................................................................33
6.4.5 Load/unload mechanism ...............................................................................................33
6.5.1 Operating vibration .......................................................................................................33
6.5.2 Nonoperating vibration .................................................................................................34
6.5.3 Operating shock ............................................................................................................34
6.5.4 Nonoperating shock ......................................................................................................35
6.5.2 Nonoperating vibration .................................................................................................34
6.5.3 Operating shock ............................................................................................................34
6.5.4 Nonoperating shock ......................................................................................................35
6.6.1 Sound power levels .......................................................................................................35
6.6.2 Discrete tone penalty ....................................................................................................36
6.6.2 Discrete tone penalty ....................................................................................................36
6.8.1 CE mark ........................................................................................................................36
6.8.2 C-TICK mark ................................................................................................................36
6.8.3 BSMI mark ...................................................................................................................36
6.8.4 MIC mark......................................................................................................................37
6.8.2 C-TICK mark ................................................................................................................36
6.8.3 BSMI mark ...................................................................................................................36
6.8.4 MIC mark......................................................................................................................37
7.1 Cabling...................................................................................................................................39
7.2 Interface connector.................................................................................................................39
7.3 Signal definitions ...................................................................................................................40
7.4 Signal descriptions .................................................................................................................41
7.5 Interface logic signal levels ...................................................................................................44
7.6 Reset timings..........................................................................................................................44
7.7 PIO timings ............................................................................................................................45
7.8 Multi word DMA timings ......................................................................................................46
7.9 Ultra DMA timings ................................................................................................................47
7.2 Interface connector.................................................................................................................39
7.3 Signal definitions ...................................................................................................................40
7.4 Signal descriptions .................................................................................................................41
7.5 Interface logic signal levels ...................................................................................................44
7.6 Reset timings..........................................................................................................................44
7.7 PIO timings ............................................................................................................................45
7.8 Multi word DMA timings ......................................................................................................46
7.9 Ultra DMA timings ................................................................................................................47
7.9.1 Initiating Read DMA ....................................................................................................47
7.9.2 Host Pausing Read DMA..............................................................................................48
7.9.3 Host Terminating Read DMA.......................................................................................49
7.9.4 Device Terminating Read DMA...................................................................................50
7.9.5 Initiating Write DMA ...................................................................................................51
7.9.6 Device Pausing Write DMA .........................................................................................52
7.9.2 Host Pausing Read DMA..............................................................................................48
7.9.3 Host Terminating Read DMA.......................................................................................49
7.9.4 Device Terminating Read DMA...................................................................................50
7.9.5 Initiating Write DMA ...................................................................................................51
7.9.6 Device Pausing Write DMA .........................................................................................52