Справочник Пользователя для Samsung S3C2440A
S3C2440A RISC MICROPROCESSOR
UART
11-1
11
UART
OVERVIEW
The S3C2440A Universal Asynchronous Receiver and Transmitter (UART) provide three independent
asynchronous serial I/O (SIO) ports, each of which can operate in Interrupt-based or DMA-based mode. In other
words, the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART. The
UART can support bit rates up to 115.2K bps using system clock. If an external device provides the UART with
UEXTCLK, then the UART can operate at higher speed. Each UART channel contains two 64-byte FIFOs for
receiver and transmitter.
asynchronous serial I/O (SIO) ports, each of which can operate in Interrupt-based or DMA-based mode. In other
words, the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART. The
UART can support bit rates up to 115.2K bps using system clock. If an external device provides the UART with
UEXTCLK, then the UART can operate at higher speed. Each UART channel contains two 64-byte FIFOs for
receiver and transmitter.
The S3C2440A UART includes programmable baud rates, infrared (IR) transmit/receive, one or two stop bit
insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.
insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.
Each UART contains a baud-rate generator, transmitter, receiver and a control unit, as shown in Figure 11-1. The
baud-rate generator can be clocked by PCLK, FCLK/n or UEXTCLK (external input clock). The transmitter and the
receiver contain 64-byte FIFOs and data shifters. Data is written to FIFO and then copied to the transmit shifter
before being transmitted. The data is then shifted out by the transmit data pin (TxDn). Meanwhile, received data is
shifted from the receive data pin (RxDn), and then copied to FIFO from the shifter.
baud-rate generator can be clocked by PCLK, FCLK/n or UEXTCLK (external input clock). The transmitter and the
receiver contain 64-byte FIFOs and data shifters. Data is written to FIFO and then copied to the transmit shifter
before being transmitted. The data is then shifted out by the transmit data pin (TxDn). Meanwhile, received data is
shifted from the receive data pin (RxDn), and then copied to FIFO from the shifter.
FEATURES
— RxD0, TxD0, RxD1, TxD1, RxD2, and TxD2 with DMA-based or interrupt-based operation
— UART Ch 0, 1, and 2 with IrDA 1.0 & 64-byte FIFO
— UART Ch 0 and 1 with nRTS0, nCTS0, nRTS1, and nCTS1
— Supports handshake transmit/receive