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Chapter 3
Hardware Overview
3-6
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Table 3-3 outlines the function and direction of the signals discussed in
detail in the remainder of this chapter.
detail in the remainder of this chapter.
Table 3-3. Signal Descriptions
Signal Name
Direction
Description
PXI_CLK10_IN
Out
This is a signal that can replace the native 10 MHz oscillator
on the PXI backplane. PXI_CLK10_IN may originate from
the onboard TCXO or from an external source.
on the PXI backplane. PXI_CLK10_IN may originate from
the onboard TCXO or from an external source.
PXI_CLK10
In
This signal is the PXI 10 MHz backplane clock. By default,
this signal is the output of the native 10 MHz oscillator in the
chassis. An NI PXIe-6672 in the System Timing Slot can
replace this signal with PXI_CLK10_IN.
this signal is the output of the native 10 MHz oscillator in the
chassis. An NI PXIe-6672 in the System Timing Slot can
replace this signal with PXI_CLK10_IN.
TCXO Clock
Out
This is the output of the 10 MHz TCXO. The TCXO is an
extremely stable and accurate frequency source.
extremely stable and accurate frequency source.
CLKIN
In
CLKIN is a signal connected to the SMB input pin of the
same name. CLKIN can serve as PXI_CLK10_IN, a phase
lock reference for the TCXO, or as a source for routing to
PXI_STAR.
same name. CLKIN can serve as PXI_CLK10_IN, a phase
lock reference for the TCXO, or as a source for routing to
PXI_STAR.
CLKOUT
Out
CLKOUT is the signal on the SMB output pin of the same
name. Either the TCXO clock, DDS clock, or PXI_CLK10
may be routed to this location.
name. Either the TCXO clock, DDS clock, or PXI_CLK10
may be routed to this location.
DDS Clock
Out
This is the output of the DDS. The DDS frequency can be
programmed with fine granularity from 1 Hz to 105 MHz.
The DDS chip automatically phase-locks to PXI_CLK10.
programmed with fine granularity from 1 Hz to 105 MHz.
The DDS chip automatically phase-locks to PXI_CLK10.
PXI_STAR <0..16>
In/Out
The PXI star trigger bus connects the System Timing Slot to
all other slots in a star configuration. The electrical paths of
each star line are closely matched to minimize intermodule
skew. An NI PXIe-6672 in System Timing Slot can route
signals to all other slots using the star trigger bus.
all other slots in a star configuration. The electrical paths of
each star line are closely matched to minimize intermodule
skew. An NI PXIe-6672 in System Timing Slot can route
signals to all other slots using the star trigger bus.
PFI <0..5>
In/Out
The Programmable Function Interface pins on the
NI PXIe-6672 route timing and triggering signals between
multiple PXI chassis. A wide variety of input and output
signals can be routed to or from the PFI lines.
NI PXIe-6672 route timing and triggering signals between
multiple PXI chassis. A wide variety of input and output
signals can be routed to or from the PFI lines.
PXI_TRIG <0..7>
In/Out
The PXI trigger bus consists of eight digital lines shared
among all slots in the PXI chassis. The NI PXIe-6672 can
route a wide variety of signals to and from these lines.
among all slots in the PXI chassis. The NI PXIe-6672 can
route a wide variety of signals to and from these lines.