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Refer to the Choosing the Type of Routing section for more information 
about the synchronization clock.

The PXI_Trig/PXI_Star synchronization clock is the same for all routing operations 

in which PXI_TRIG <0..7> or PXI_STAR <0..16> is defined as the output, although the 
divide-down ratio for this clock (full rate, first divider, second divider) may be chosen on 
a per route basis.

There are up to 17 PXI star triggers per chassis. Each trigger line 
is a dedicated connection between the System Timing Slot and one other 
slot. The PXI Specification, Revision 2.1, requires that the propagation 
delay along each star trigger line be matched to within 1 ns. A typical upper 
limit for the skew in most NI PXI chassis is 500 ps. The low skew of the 
PXI star trigger bus is useful for applications that require triggers to arrive 
at several modules nearly simultaneously.

The star trigger lines are bidirectional, so signals can be sent to System 
Timing Slot from a module in another slot or from System Timing Slot to 
the other module.

You can independently select the output signal source for each PXI star 
trigger line from one of the following sources:

•

PFI <0..5>

•

PXI triggers <0..7> (PXI_TRIG <0..7>)

•

Another PXI star trigger line (PXI_STAR <0..16>)

•

Global software trigger

•

PXI_Trig/PXI_Star synchronization clock

•

CLKIN

Refer to the 

 section for more information on the 

PXI_Trig/PXI_Star synchronization clock.

The NI PXIe-6672 routes signals in one of two ways: asynchronously or 
synchronously. The following sections describe the two routing types and 
the considerations for choosing each type.