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the second clock cycle. However, by synchronizing the signal, you can 
eliminate the ambiguity, and the signal will always be seen in the second 
clock cycle.

One useful feature of synchronous routing is that the signal can be 
propagated on either the rising or falling edge of the synchronization clock. 
In addition, the polarity of the destination signal can be inverted, which is 
useful when handling active-low digital signals.

Possible sources for synchronous routing include the following sources:

•

Any front panel PFI pin

•

Any PXI star trigger line (PXI_STAR <0..16>)

•

Any PXI trigger line (PXI_TRIG <0..7>)

•

Global software trigger

•

The synchronization clock itself

The possible destinations for a synchronous route are identical to those for an 

asynchronous route. The destinations include any front panel PFI pin, any PXI star trigger 
line, or any PXI trigger line.

The synchronization clock for a synchronous route can be any of the 
following signals:

•

10 MHz PXI backplane clock signal

•

DDS clock on the NI PXIe-6672

•

Front panel PFI 0 Input

•

One of two “divided copies” of any of the previously listed three 
signals. The NI PXIe-6672 includes two clock-divider circuits that can 
divide the synchronization clock signals by any power of 2 up to 512.

Refer to Figures 3-3 and 3-4 for an illustration of how the NI PXIe-6672 
performs synchronous routing operations.

The global software trigger is a single pulse with programmable delay that 
is fired on a software command. This signal is always routed synchronously 
with a clock. Therefore, asynchronous routing is not supported when the 
signal source is the global software trigger.

The software trigger can be delayed by up to 15 clock cycles on a per route 
basis. This feature is useful if a single pulse must be sent to several