Справочник Пользователя для National Instruments NI 781xR

Do not drive the same PXI local bus line with the NI PXI-781xR and another 

device simultaneously. Such signal driving can damage both devices. NI is not liable for 
any damage resulting from such signal driving.

The NI PXI-781xR local bus lines are compatible only with 3.3 V signaling 
LVTTL and LVCMOS levels.

Do not enable the local bus lines on an adjacent device if the device drives 

anything other than 0–3.3 V LVTTL signal levels on the NI PXI-781xR. Enabling the lines 
in this way can damage the NI PXI-781xR. NI is not liable for any damage resulting from 
enabling such lines.

The left local bus lines from the left peripheral slot of a PXI backplane 
(Slot 2) are routed to the star trigger lines of up to 13 other peripheral slots 
in a two-segment PXI system. This configuration provides a dedicated, 
delay-matched trigger signal between the first peripheral slot and the 
other peripheral slots and results in very precise trigger timing signals. 
For example, an NI PXI-781xR in Slot 2 can send an independent 
trigger signal to each device plugged into Slots <3..15> using the 
PXI/LBLSTAR<0..12>. Each device receives its trigger signal on its own 
dedicated star trigger line.

Do not configure the NI PXI-781xR and another device to drive the same physical 

star trigger line simultaneously. Such signal driving can damage the NI PXI-781xR and the 
other device. NI is not liable for any damage resulting from such signal driving.

Refer to the PXI Hardware Specification Revision 2.1 and PXI Software 
Specification Revision 2.1 at 

www.pxisa.org

 for more information about 

PXI triggers.

Refer to Figure 2-3 for the location of the switches on the NI 781xR. For 
normal operation, SW1 is in the OFF position. To prevent a VI stored in 
flash memory from loading to the FPGA at power up, move SW1 to the 
ON position, as shown in Figure 2-5.

SW2 and SW3 are not connected.