Справочник Пользователя для Emerson CC1000DM
P M C / P C I I N T E R F A C E
PMC Module Installation
3-4
3
The Internal Arbiter Control register is located at offset 50h. All bits are read/write.
LPGF:
Low Priority Group Fixed arbitration
1
1
Uses the fixed priority arbitration scheme
0
Uses the rotating priority arbitration scheme (default)
LPGA:
Low Priority Group Arbitration order
This bit is only valid when the low priority arbitration group is set to a fixed arbitration
scheme (relative to HPM).
1
This bit is only valid when the low priority arbitration group is set to a fixed arbitration
scheme (relative to HPM).
1
Priority decreases in ascending numbers of the master
0
Priority increases in ascending numbers of the master (default)
HPGF:
High Priority Group Fixed arbitration
1
1
Uses the fixed priority arbitration scheme
0
Uses the rotating priority arbitration scheme (default)
HPGA:
High Priority Group Arbitration order
This bit is only valid when the high priority arbitration group is set to a fixed arbitra-
tion scheme (relative to HPM).
1
This bit is only valid when the high priority arbitration group is set to a fixed arbitra-
tion scheme (relative to HPM).
1
Priority decreases in ascending numbers of the master
0
Priority increases in ascending numbers of the master (default)
HPMLP:
Highest Priority Master in Low Priority group
This controls which master in the low priority group has the highest priority (only for
fixed arbitration scheme).
0000
This controls which master in the low priority group has the highest priority (only for
fixed arbitration scheme).
0000
Master#0 has highest priority (default)
0001
Master#1 has highest priority
to…
1001
1001
PCI 6254 has highest priority
1010-1111
reserved
HPMHP:
Highest Priority Master in High Priority group
This controls which master in the high priority group has the highest priority. It is valid
only in the fixed arbitration scheme.
0000
This controls which master in the high priority group has the highest priority. It is valid
only in the fixed arbitration scheme.
0000
Master#0 has highest priority (default)
0001
Master#1 has highest priority
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BPC
HPMHP
HPMLP
HPG
A
HPG
F
LPG
A
LPG
F
Register 3-1:
Internal Arbiter Control Register