Справочник Пользователя для IBM uPD78P083

This section describes CPU clock switching procedure.

(1) The CPU is reset by setting the RESET signal to low level after power-on.  After that, when reset is released

by setting the RESET signal to high level, main system clock starts oscillation.  At this time, oscillation

stabilization time (2

17

/f

X

) is secured automatically.

After that, the CPU starts executing the instruction at the minimum speed of the main system clock (12.8 

µ

s when

operated at 5.0 MHz).

(2) After the lapse of a sufficient time for the V

DD

 voltage to increase to enable operation at maximum speeds,

the processor clock control register (PCC) and oscillation mode selection register (OSMS) are rewritten and

the maximum-speed operation is carried out.

V

DD

RESET

CPU Clock

Wait (26.2 ms : 5.0 MHz)

Internal Reset Operation

Minimum
Speed
Operation

Maximum Speed
Operation