Справочник Пользователя для IBM uPD78P083
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CHAPTER 3 CPU ARCHITECTURE
3.4.6 Register indirect addressing
[Function]
This addressing addresses the memory with the contents of a register pair specified as an operand. The register
pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code
in an instruction code. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
Description
—
[DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code
1 0 0 0 0 1 0 1
[Illustration]
16
0
8
D
7
E
0
7
7 0
A
DE
Memory
Contents of addressed
memory are transferred.
memory are transferred.
Memory address specified
by register pair DE
by register pair DE