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6024E
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Contents
6023E/6024E/6025E User Manual
viii
ni.com
Figures
Figure 1-1.
The Relationship Between the Programming Environment,
NI-DAQ, and Your Hardware............................................................... 1-5
Figure 3-1.
PCI-6023E, PCI-6024E, PCI-6025E, and PXI-6025E
Block Diagram ...................................................................................... 3-1
Figure 3-2.
DAQCard-6024E Block Diagram......................................................... 3-2
Figure 3-3.
Dithering ............................................................................................... 3-5
Figure 3-4.
CONVERT* Signal Routing................................................................. 3-8
Figure 3-5.
PCI RTSI Bus Signal Connection......................................................... 3-10
Figure 3-6.
PXI RTSI Bus Signal Connection......................................................... 3-11
Figure 4-1.
I/O Connector Pin Assignment for the 6023E/6024E........................... 4-2
Figure 4-2.
I/O Connector Pin Assignment for the 6025E ...................................... 4-3
Figure 4-3.
Programmable Gain Instrumentation Amplifier (PGIA) ...................... 4-10
Figure 4-4.
Summary of Analog Input Connections ............................................... 4-12
Figure 4-5.
Differential Input Connections for Ground-Referenced Signals .......... 4-14
Figure 4-6.
Differential Input Connections for Nonreferenced Signals .................. 4-15
Figure 4-7.
Single-Ended Input Connections for Nonreferenced or
Floating Signals .................................................................................... 4-18
Figure 4-8.
Single-Ended Input Connections for Ground-Referenced Signals ....... 4-19
Figure 4-9.
Analog Output Connections.................................................................. 4-20
Figure 4-10.
Digital I/O Connections ........................................................................ 4-21
Figure 4-11.
Digital I/O Connections Block Diagram............................................... 4-22
Figure 4-12.
DIO Channel Configured for High DIO Power-up State with
External Load........................................................................................ 4-24
Figure 4-13.
Timing Specifications for Mode 1 Input Transfer ................................ 4-27
Figure 4-14.
Timing Specifications for Mode 1 Output Transfer ............................. 4-28
Figure 4-15.
Timing Specifications for Mode 2 Bidirectional Transfer.................... 4-29
Figure 4-16.
Timing I/O Connections ....................................................................... 4-31
Figure 4-17.
Typical Posttriggered Acquisition ........................................................ 4-32
Figure 4-18.
Typical Pretriggered Acquisition .......................................................... 4-33
Figure 4-19.
SCANCLK Signal Timing .................................................................... 4-33
Figure 4-20.
EXTSTROBE* Signal Timing ............................................................. 4-34
Figure 4-21.
TRIG1 Input Signal Timing.................................................................. 4-34
Figure 4-22.
TRIG1 Output Signal Timing ............................................................... 4-35
Figure 4-23.
TRIG2 Input Signal Timing.................................................................. 4-36
Figure 4-24.
TRIG2 Output Signal Timing ............................................................... 4-36
Figure 4-25.
STARTSCAN Input Signal Timing...................................................... 4-37
Figure 4-26.
STARTSCAN Output Signal Timing ................................................... 4-37
Figure 4-27.
CONVERT* Input Signal Timing ........................................................ 4-38
Figure 4-28.
CONVERT* Output Signal Timing...................................................... 4-39
Figure 4-29.
SISOURCE Signal Timing ................................................................... 4-40
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