Справочник Пользователя для Intel 253668-032US
Vol. 3 17-21
8086 EMULATION
2. Store the EFLAGS (low-order 16 bits only), CS and EIP values of the 8086
program on the privilege-level 3 stack. This is the stack that the virtual-8086-
mode task is using. (The 8086 handler may use or modify this information.)
mode task is using. (The 8086 handler may use or modify this information.)
3. Change the return link on the privilege-level 0 stack to point to the privilege-level
3 handler procedure.
4. Execute an IRET instruction to pass control to the 8086 program handler.
5. When the IRET instruction from the privilege-level 3 handler triggers a general-
5. When the IRET instruction from the privilege-level 3 handler triggers a general-
protection exception (#GP) and thus effectively again calls the virtual-8086
monitor, restore the return link on the privilege-level 0 stack to point to the
original, interrupted, privilege-level 3 procedure.
monitor, restore the return link on the privilege-level 0 stack to point to the
original, interrupted, privilege-level 3 procedure.
6. Copy the low order 16 bits of the EFLAGS image from the privilege-level 3 stack
to the privilege-level 0 stack (because some 8086 handlers modify these flags to
return information to the code that caused the interrupt).
return information to the code that caused the interrupt).
7. Execute an IRET instruction to pass control back to the interrupted 8086
program.
Note that if an operating system intends to support all 8086 MS-DOS-based
programs, it is necessary to use the actual 8086 interrupt and exception handlers
supplied with the program. The reason for this is that some programs modify their
own interrupt vector table to substitute (or hook in series) their own specialized
interrupt and exception handlers.
programs, it is necessary to use the actual 8086 interrupt and exception handlers
supplied with the program. The reason for this is that some programs modify their
own interrupt vector table to substitute (or hook in series) their own specialized
interrupt and exception handlers.
17.3.1.3 Handling an Interrupt or Exception Through a Task Gate
When an interrupt or exception vector points to a task gate in the IDT, the processor
performs a task switch to the selected interrupt- or exception-handling task. The
following actions are carried out as part of this task switch:
1. The EFLAGS register with the VM flag set is saved in the current TSS.
2. The link field in the TSS of the called task is loaded with the segment selector of
performs a task switch to the selected interrupt- or exception-handling task. The
following actions are carried out as part of this task switch:
1. The EFLAGS register with the VM flag set is saved in the current TSS.
2. The link field in the TSS of the called task is loaded with the segment selector of
the TSS for the interrupted virtual-8086-mode task.
3. The EFLAGS register is loaded from the image in the new TSS, which clears the
VM flag and causes the processor to switch to protected mode.
4. The NT flag in the EFLAGS register is set.
5. The processor begins executing the selected interrupt- or exception-handler
5. The processor begins executing the selected interrupt- or exception-handler
task.
When an IRET instruction is executed in the handler task and the NT flag in the
EFLAGS register is set, the processors switches from a protected-mode interrupt- or
exception-handler task back to a virtual-8086-mode task. Here, the EFLAGS and
segment registers are loaded from images saved in the TSS for the virtual-8086-
mode task. If the VM flag is set in the EFLAGS image, the processor switches back to
virtual-8086 mode on the task switch. The CPL at the time the IRET instruction is
EFLAGS register is set, the processors switches from a protected-mode interrupt- or
exception-handler task back to a virtual-8086-mode task. Here, the EFLAGS and
segment registers are loaded from images saved in the TSS for the virtual-8086-
mode task. If the VM flag is set in the EFLAGS image, the processor switches back to
virtual-8086 mode on the task switch. The CPL at the time the IRET instruction is