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PC Processors (Intel Celeron M)
Code name
Messaging
Messaging
Micro-architecture
MMX
MMX
™ / Streaming SIMD
SSE2
Power mgmt technology
Power mgmt technology
L1 cache - bus
L1 data cache
L1 instruction cache
L1 data cache
L1 instruction cache
L2 cache - size
L2 cache - data path
L3 cache
L2 cache - data path
L3 cache
System bus
Memory addressability
System bus - width
Memory addressability
System bus - width
Execution units
Out-of-order instructions
Branch prediction
Speculative execution
Math coprocessor
Out-of-order instructions
Branch prediction
Speculative execution
Math coprocessor
Compatibility
Multiple processors
Multiple processors
Technology (micron)
Package and connector
Package and connector
Frequency (MHz/GHz)
and available date
and available date
Chipset support
All trademarks are the property of their respective owners
© IBM Corp.
(33INTEL) Compiled by Roger Dodson, IBM. January 2004
Banias Celeron or ICP-M
Based on an architecture designed specifically for mobile computing, the Intel Celeron M processor delivers a balanced
level of mobile processor technology and exceptional value in sleeker, lighter notebook designs
IA-32 / micro-op fusion, dedicated stack manager, advanced branch prediction, power-optimized processor system bus
MMX
Based on an architecture designed specifically for mobile computing, the Intel Celeron M processor delivers a balanced
level of mobile processor technology and exceptional value in sleeker, lighter notebook designs
IA-32 / micro-op fusion, dedicated stack manager, advanced branch prediction, power-optimized processor system bus
MMX
™ (57 new instructions) / Streaming SIMD Extensions (70 new instructions)
Streaming SIMD Extensions 2 (144 new instructions)
Auto Halt, Stop Grant, Deep Sleep, Deeper Sleep
Auto Halt, Stop Grant, Deep Sleep, Deeper Sleep
256-bit data path / full speed
32KB data cache / integrated
32KB instruction cache / integrated
32KB data cache / integrated
32KB instruction cache / integrated
512KB / full speed (Advanced Transfer Cache)
256-bit data path (32 bytes) / 64 byte cache line size / 8-way set associative / integrated / unified (internal die; on die)
None
256-bit data path (32 bytes) / 64 byte cache line size / 8-way set associative / integrated / unified (internal die; on die)
None
400MHz (transfers data four times per clock) / address bus transfers at two times per clock / 64 byte cache line size
64GB memory addressability / 36-bit addressing / address bus is double clocked at 200MHz
64-bit data path
64GB memory addressability / 36-bit addressing / address bus is double clocked at 200MHz
64-bit data path
2 integer units; 1 floating point units; 1 load unit; 1 store unit
Yes (out-of-order instruction execution)
Dynamic (based on history)
Yes (Advanced Dynamic Execution)
Pipelined floating point unit
Yes (out-of-order instruction execution)
Dynamic (based on history)
Yes (Advanced Dynamic Execution)
Pipelined floating point unit
Compatible with IA-32 software
No SMP support
No SMP support
0.13u
Micro Flip-Chip Pin Grid Array (Micro-FCPGA) requires 479-pin surface mount Zero Insertion Force (ZIF) socket
(mPGA479M socket) or Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball)
Micro Flip-Chip Pin Grid Array (Micro-FCPGA) requires 479-pin surface mount Zero Insertion Force (ZIF) socket
(mPGA479M socket) or Micro Flip-Chip Ball Grid Array (Micro-FCBGA) for surface mount (479-ball)
Voltage Thermal Design Power Announce
date
800MHz Ultra Low Voltage
1.004 volts
7 watts
January 2004
1.2GHz
1.356 volts
24.5 watts
January 2004
1.3GHz
1.356 volts
24.5 watts
January 2004
Intel 855 chipset family
Intel 852GM
Other compatible chipsets
Intel 852GM
Other compatible chipsets
Intel
®
Celeron
®
M processor for mobile systems
Created by IBM PC Institute
Personal Systems Reference (PSREF)