Справочник Пользователя для Infineon DDR3 2GB Memory Module IMSH2GU13A1F1C-10F
Модели
IMSH2GU13A1F1C-10F
IMSH[1G/2G][U/E]x3A1F1C(T)
DDR3 Unbuffered DIMM
Advance Internet Data Sheet
Rev. 0.65, 2008-12
15
03052008-R2G5-2FN2
4
Speed Bins
AC timings are provided with CK/CK and DQS/DQS
differential slew rate of 2.0 V/ns. Timings are further provided
for calibrated OCD drive strength. The CK/CK input reference
level (for timing referenced to CK / CK) is the point at which
CK and CK cross.The DQS/DQS reference level (for timing
referenced to DQS/DQS) is the point at which DQS and DQS
differential slew rate of 2.0 V/ns. Timings are further provided
for calibrated OCD drive strength. The CK/CK input reference
level (for timing referenced to CK / CK) is the point at which
CK and CK cross.The DQS/DQS reference level (for timing
referenced to DQS/DQS) is the point at which DQS and DQS
cross.Inputs are not recognized as valid until
V
REF
stabilizes.
During the period before
V
REF.CA
and
V
REFDQ
stabilizes, CKE
= 0.2 x
V
DDQ
is recognized as low. The output timing reference
voltage level is
V
TT
.For details of all relevant AC timing
parameters see the QIMONDA DDR3 component datasheet.
4.1
Speed Bins
The following tables show DDR3 speed bins and relevant
timing parameters. Other timing parameters are provided in
the following chapter.
timing parameters. Other timing parameters are provided in
the following chapter.
The absolute specification for all speed bins is
T
OPER
and
V
DD
=
V
DDQ
= 1.5 V +/-0.075 V. In addition the following
general notes apply.
General Notes for Speed Bins:
• The CL setting and CWL setting result in
t
CK.AVG.MIN
and
t
CK.AVG.MAX
requirements. When making a selection of
t
CK.AVG
, both need to be fulfiled: Requirements from CL
setting as well as requirements from CWL setting.
•
t
CK.AVG.MIN
limits: Since CAS Latency is not purely analog -
data and strobe output are synchronized by the DLL - all
possible intermediate frequencies may not be provided. An
application should use the next smaller standard
possible intermediate frequencies may not be provided. An
application should use the next smaller standard
t
CK.AVG
value (2.5, 1.875, 1.5, 1.25 , 1.07, or 0.935 ns) when
calculating CL [nCK] =
calculating CL [nCK] =
t
AA
[ns] /
t
CK.AVG
[ns], rounding up to
the next ‘Supported CL’.
•
t
CK.AVG.MAX
limits: Calculate
t
CK.AVG
=
t
AA.MAX
/
CLSELECTED and round the resulting
t
CK.AVG
down to the
next valid speed bin limit (i.e. 3.3 ns or 2.5 ns or 1.875 ns
1.5ns or 1.25ns or 1.07 ns or 0.935ns). This result is
1.5ns or 1.25ns or 1.07 ns or 0.935ns). This result is
t
CK.AVG.MAX
corresponding to CLSELECTED.
• ‘Reserved’ settings are not allowed. User must program a
different value.
• Downbinning support for DDR3-1333H and DDR3-1600K
parts: The minimum tAA / tRCD / tRP supported by DDR3-
1333H and DDR3-1600K devices is 13.125ns. Therefore,
1333H and DDR3-1600K devices is 13.125ns. Therefore,
in module application, tAA / tRCD / tRP should be
programmed with minimum supported values. For
example, DDR3-1333H supporting down-shift to DDR3-
1066F should program SPD as 13.125ns for tAA.MIN
(Byte16)/tRCD.MIN (Byte18) / tRP (Byte20). DDR3-1600K
supporting down-shift to DDR3-1333H and to DDR3-
1066F should program SPD as 13.125ns for tAA.MIN
(Byte16)/tRCD.MIN (Byte18) / tRP (Byte20).
programmed with minimum supported values. For
example, DDR3-1333H supporting down-shift to DDR3-
1066F should program SPD as 13.125ns for tAA.MIN
(Byte16)/tRCD.MIN (Byte18) / tRP (Byte20). DDR3-1600K
supporting down-shift to DDR3-1333H and to DDR3-
1066F should program SPD as 13.125ns for tAA.MIN
(Byte16)/tRCD.MIN (Byte18) / tRP (Byte20).
• Any DDR3-1066 speed bin also supports functional
operation at lower frequencies as shown in the tables
which are not subject to Production Tests but verified by
Design/Characterization.
which are not subject to Production Tests but verified by
Design/Characterization.
• Any DDR3-1333 speed bin also supports functional
operation at lower frequencies as shown in the tables
which are not subject to Production Tests but verified by
Design/Characterization.
which are not subject to Production Tests but verified by
Design/Characterization.
• Any DDR3-1600 speed bin also supports functional
operation at lower frequencies as shown in the tables
which are not subject to Production Tests but verified by
Design/Characterization.
which are not subject to Production Tests but verified by
Design/Characterization.