Справочник Пользователя для Renesas SH7264
Section 25 NAND Flash Memory Controller
Page 1326 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
(2) NAND-Type Flash Memory (2048 + 64 Bytes) Access
Figure 25.7 shows an example of read operation for NAND-type flash memory (2048 + 64 bytes).
In this example, the first command is specified as H'00, the second command is specified as H'30,
and address data length is specified as 4 bytes. The number of read bytes is specified as 4 bytes in
the data counter.
In this example, the first command is specified as H'00, the second command is specified as H'30,
and address data length is specified as 4 bytes. The number of read bytes is specified as 4 bytes in
the data counter.
CLE
ALE
WE
RE
I/O7 to I/O0
R/B
H'00
A1 A2 A3 A4
1
2
3
4
H'30
Figure 25.7 Read Operation Timing for NAND-Type Flash Memory
Figures 25.8 and 25.9 show examples of programming operation for NAND-type flash memory
(2048 + 64 bytes).
(2048 + 64 bytes).
CLE
ALE
WE
RE
I/O7 to I/O0
R/B
H'80
A1 A2 A3 A4
1
2
3
4
H'10
Figure 25.8 Programming Operation Timing for NAND-Type Flash Memory (1)