Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333

Datasheet

139

B/D/F/Type:

0/0/0/MCHBAR

Address Offset: CF1h

Default Value:

00h

Access:

RO, RW 

Size:

8 bits

This register selects specific errors to generate a SMI DMI special cycle, as enabled by 

the Device 0 SMI Error Command Register [SMI on MCH Thermal Sensor Trip]. The SMI 

must not be enabled at the same time as the SERR/SCI for the thermal sensor event.

All bits in this register are reset to their defaults by PLTRST#.

7:3

RO

00h

Reserved

2

RW

0b

SMI on MCH Catastrophic Thermal Sensor Trip (SMGCTST): 
1 = Does not mask the generation of an SMI DMI special cycle on a catastrophic 

thermal sensor trip.

0 = Disable reporting of this condition via SMI messaging.

1

RW

0b

SMI on MCH Hot Thermal Sensor Trip (SMGHTST): 
1 = Does not mask the generation of an SMI DMI special cycle on a Hot thermal 

sensor trip.

0 = Disable reporting of this condition via SMI messaging.

0

RW

0b

SMI on MCH Aux Thermal Sensor Trip (SMGATST): 
1 = Does not mask the generation of an SMI DMI special cycle on an Auxiliary 

thermal sensor trip.

0 = Disable reporting of this condition via SMI messaging.