Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333

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Datasheet

B/D/F/Type:

0/3/3/KT MM/IO

Address Offset: 6h

Default Value:

00h

Access:

RO, RO/CR 

Size:

8 bits

The functionality of the Modem is emulated by the FW. This register provides the status 

of the current state of the control lines from the modem. 

Reset: Host system Reset or D3->D0 transition.

B/D/F/Type:

0/3/3/KT MM/IO

Address Offset: 7h

Default Value:

00h

Access:

RW 

Size:

8 bits

This register has no affect on hardware. This is for the programmer to hold data 

temporarily.

Reset: Host system reset or D3->D0 transition

7

RO

0b

Data Carrier Detect (DCD): In Loop Back mode this bit is connected by 
hardware to the value of MCR bit 3

6

RO

0b

Ring Indicator (RI): In Loop Back mode this bit is connected by hardware to 
the value of MCR bit 2.

5

RO

0b

Data Set Ready (DSR): In Loop Back mode this bit is connected by hardware 
to the value of MCR bit 0.

4

RO

0b

Clear To Send (CTS): In Loop Back mode this bit is connected by hardware to 
the value of MCR bit 1.

3

RO/CR

0b

Delta Data Carrier Detect (DDCD): This bit is set when bit 7 is changed. This 
bit is cleared by hardware when the MSR register is being read by the HOST 
driver.

2

RO/CR

0b

Trailing Edge of Read Detector (TERI): This bit is set when bit 6 is changed 
from 1 to 0. This bit is cleared by hardware when the MSR register is being read 
by the Host driver.

1

RO/CR

0b

Delta Data Set Ready (DDSR): This bit is set when bit 5 is changed. This bit is 
cleared by hardware when the MSR register is being read by the Host driver.

0

RO/CR

0b

Delta Clear To Send (DCTS): This bit is set when bit 4 is changed. This bit is 
cleared by hardware when the MSR register is being read by the Host driver.

7:0

RW

00h