Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333

260

Datasheet

B/D/F/Type:

0/0/0/DMIBAR

Address Offset: 0–3h

Default Value:

04010002h

Access:

RO

Size:

32 bits

This register indicates DMI Virtual Channel capabilities.

B/D/F/Type:

0/0/0/DMIBAR

Address Offset: 4–7h

Default Value:

00000001h

Access:

RWO, RO 

Size:

32 bits

This register describes the configuration of PCI Express Virtual Channels associated 

with this port.

31:20

RO

040h

Pointer to Next Capability (PNC): This field contains the offset to the next 
PCI Express capability structure in the linked list of capabilities (Link Declaration 
Capability).

19:16

RO

1h

PCI Express Virtual Channel Capability Version (PCIEVCCV): Hardwired 
to 1 to indicate compliances with the 1.1 version of the PCI Express 
specification.
Note: This version does not change for 2.0 compliance.

15:0

RO

0002h

Extended Capability ID (ECID): Value of 0002 h identifies this linked list item 
(capability structure) as being for PCI Express Virtual Channel registers.

31:7

RO

0000000h Reserved 

6:4

RO

000b

Low Priority Extended VC Count (LPEVCC): Indicates the number of 
(extended) Virtual Channels in addition to the default VC belonging to the low-
priority VC (LPVC) group that has the lowest priority with respect to other VC 
resources in a strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.

3

RO

0b

Reserved 

2:0

RWO

001b

Extended VC Count (EVCC): Indicates the number of (extended) Virtual 
Channels in addition to the default VC supported by the device.
The Private Virtual Channel is not included in this count.