Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333

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Datasheet

• Device 3 

— ME  Control

• Device 6, Function 0 (Intel 3210 MCH only)

— MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window. 
— PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
— PMUBASE/PMULIMIT – PCI Express port upper prefetchable memory access 

window

— IOBASE1/IOLIMIT1 – PCI Express port I/O access window.

The rules for the above programmable ranges are: 

1. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or 

system designers' responsibility to limit memory population so that adequate PCI, 

PCI Express, High BIOS, and PCI Express Memory Mapped space, and APIC 

memory space can be allocated.

2. In the case of overlapping ranges with memory, the memory decode will be given 

priority. This is an Intel Trusted Execution Technology requirement. It is necessary 

to get Intel TET protection checks, avoiding potential attacks.

3. There are NO Hardware Interlocks to prevent problems in the case of overlapping 

ranges.

4. Accesses to overlapped ranges may produce indeterminate results. 
5. The only peer-to-peer cycles allowed below the top of Low Usable memory (register 

TOLUD) are DMI Interface to PCI Express range writes.

 represents system memory address map in a simplified form.