Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333
Модели
P4X-UPE3210-316-6M1333
4
Datasheet
I/O Address Space .............................................................................................52
3.9.1
3.9.1
MCH Register Description.........................................................................................55
4.1
4.1
Routing Configuration Accesses ...........................................................................60
4.4.1
4.4.1
DRAM Controller Registers (D0:F0) ..........................................................................65
5.1
5.1
PCISTS—PCI Status ................................................................................69
5.1.10 SID—Subsystem Identification..................................................................71
5.1.11 CAPPTR—Capabilities Pointer....................................................................72
5.1.12 PXPEPBAR—PCI Express* Egress Port Base Address ....................................72
5.1.13 MCHBAR—MCH Memory Mapped Register Range Base .................................73
5.1.14 DEVEN—Device Enable ............................................................................74
5.1.15 PCIEXBAR—PCI Express* Register Range Base Address ...............................75
5.1.16 DMIBAR—Root Complex Register Range Base Address .................................77
5.1.17 PAM0—Programmable Attribute Map 0.......................................................78
5.1.18 PAM1—Programmable Attribute Map 1.......................................................79
5.1.19 PAM2—Programmable Attribute Map 2.......................................................80
5.1.20 PAM3—Programmable Attribute Map 3.......................................................81
5.1.21 PAM4—Programmable Attribute Map 4.......................................................82
5.1.22 PAM5—Programmable Attribute Map 5.......................................................83
5.1.23 PAM6—Programmable Attribute Map 6.......................................................84
5.1.24 LAC—Legacy Access Control .....................................................................84
5.1.25 REMAPBASE—Remap Base Address Register...............................................85
5.1.26 REMAPLIMIT—Remap Limit Address Register ..............................................85
5.1.27 SMRAM—System Management RAM Control................................................86
5.1.28 ESMRAMC—Extended System Management RAM Control ..............................87
5.1.29 TOM—Top of Memory ..............................................................................88
5.1.30 TOUUD—Top of Upper Usable Dram ..........................................................88
5.1.31 BSM—Base of Stolen Memory ...................................................................89
5.1.32 TSEGMB—TSEG Memory Base ..................................................................89
5.1.33 TOLUD—Top of Low Usable DRAM .............................................................90
5.1.11 CAPPTR—Capabilities Pointer....................................................................72
5.1.12 PXPEPBAR—PCI Express* Egress Port Base Address ....................................72
5.1.13 MCHBAR—MCH Memory Mapped Register Range Base .................................73
5.1.14 DEVEN—Device Enable ............................................................................74
5.1.15 PCIEXBAR—PCI Express* Register Range Base Address ...............................75
5.1.16 DMIBAR—Root Complex Register Range Base Address .................................77
5.1.17 PAM0—Programmable Attribute Map 0.......................................................78
5.1.18 PAM1—Programmable Attribute Map 1.......................................................79
5.1.19 PAM2—Programmable Attribute Map 2.......................................................80
5.1.20 PAM3—Programmable Attribute Map 3.......................................................81
5.1.21 PAM4—Programmable Attribute Map 4.......................................................82
5.1.22 PAM5—Programmable Attribute Map 5.......................................................83
5.1.23 PAM6—Programmable Attribute Map 6.......................................................84
5.1.24 LAC—Legacy Access Control .....................................................................84
5.1.25 REMAPBASE—Remap Base Address Register...............................................85
5.1.26 REMAPLIMIT—Remap Limit Address Register ..............................................85
5.1.27 SMRAM—System Management RAM Control................................................86
5.1.28 ESMRAMC—Extended System Management RAM Control ..............................87
5.1.29 TOM—Top of Memory ..............................................................................88
5.1.30 TOUUD—Top of Upper Usable Dram ..........................................................88
5.1.31 BSM—Base of Stolen Memory ...................................................................89
5.1.32 TSEGMB—TSEG Memory Base ..................................................................89
5.1.33 TOLUD—Top of Low Usable DRAM .............................................................90