Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333

72

Datasheet

B/D/F/Type:

0/0/0/PCI

Address Offset: 34h

Default Value:

E0h

Access:

RO 

Size:

8 bits

The CAPPTR provides the offset that is the pointer to the location of the first device 

capability in the capability list.

B/D/F/Type:

0/0/0/PCI

Address Offset: 40–47h

Default Value:

0000000000000000h

Access:

RO, RW/L 

Size:

64 bits

This is the base address for the PCI Express Egress Port MMIO Configuration space. 

There is no physical memory within this 4 KB window that can be addressed. The 4 KB 

reserved by this register does not alias to any PCI 2.3 compliant memory mapped 

space. On reset, the EGRESS port MMIO configuration space is disabled and must be 

enabled by writing a 1 to PXPEPBAREN [Dev 0, offset 40h, bit 0] 

All the bits in this register are locked in Intel

®

 TXT mode.

7:0

RO

E0h

Capabilities Pointer (CAPPTR): Pointer to the offset of the first capability ID 
register block. In this case the first capability is the product-specific Capability 
Identifier (CAPID0).

63:36

RO

0000000h Reserved

35:12

RW/L

000000h

PCI Express Egress Port MMIO Base Address (PXPEPBAR): This field 
corresponds to bits 35 to 12 of the base address PCI Express Egress Port 
MMIO configuration space. BIOS will program this register resulting in a base 
address for a 4 KB block of contiguous memory address space. This register 
ensures that a naturally aligned 4KB space is allocated within the first 64 GB 
of addressable memory space. System Software uses this base address to 
program the MCH MMIO register set. All the bits in this register are locked in 
Intel TXT mode.

11:1

RO

000h

Reserved

0

RW/L

0b

PXPEPBAR Enable (PXPEPBAREN): 
0 = PXPEPBAR is disabled and does not claim any memory
1 = PXPEPBAR memory mapped accesses are claimed and decoded 

appropriately

This register is locked by Intel TXT.