Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333
Модели
P4X-UPE3210-316-6M1333
Datasheet
95
DRAM Controller Registers (D0:F0)
5.1.38
CAPID0—Capability Identifier
B/D/F/Type:
0/0/0/PCI
Address Offset:
E0–EBh
Default Value:
00000001C1064000010C0009h
Access:
RO
Size:
96 bits
BIOS Optimal Default
0h
This register provides control of bits in this register are only required for customer
visible component differentiation.
Bit
Access
Default
Value
Description
95:78
RO
0s
Reserved
77
RO
0b
Dual Channel Disable (DCD): Disables dual-channel operation
0 = Dual channel operation allowed
1 = Only single channel operation allowed - Only channel 0 will operate, channel
0 = Dual channel operation allowed
1 = Only single channel operation allowed - Only channel 0 will operate, channel
1 will be turned off and tristated to save power. This setting hardwires the
rank population field for channel 1 to zero. (MCHBAR offset 660h, bits
20:23).
rank population field for channel 1 to zero. (MCHBAR offset 660h, bits
20:23).
76
RO
0b
2 DIMMS per Channel Disable (2DPCD): Allows Dual-Channel operation but
only supports 1 DIMM per channel.
0 = 2 DIMMs per channel Enabled
1 = 2 DIMMs per channel disabled. This setting hardwires bits 2 and 3 of the
only supports 1 DIMM per channel.
0 = 2 DIMMs per channel Enabled
1 = 2 DIMMs per channel disabled. This setting hardwires bits 2 and 3 of the
rank population field for each channel to zero. (MCHBAR offset 260h, bits
22:23 for channel 0 and MCHBAR offset 660h, bits 22:23 for channel 1).
22:23 for channel 0 and MCHBAR offset 660h, bits 22:23 for channel 1).
75
RO
0b
Chipset Intel TXT disable (LTDIS): Chipset Intel TXT disable
74:75
RO
00b
Reserved
72
RO
0b
Agent Presence Disable (APD):
71
RO
0b
Circuit Breaker Disable (CBD):
70
RO
0b
Multiprocessor Disable (MD):
0 = MCH capable of Multiple Processors
1 = MCH capable of uni-processor only.
0 = MCH capable of Multiple Processors
1 = MCH capable of uni-processor only.
69
RO
0b
FAN Speed Control Disable (FSCD):
68
RO
0b
EastFork Disable (EFD):
67:65
RO
000b
Reserved
64:62
RO
111b
Reserved
61:58
RO
0000b
Reserved
57
RO
0b
ME Disable (MED):
0 = ME feature is enabled
1 = ME feature is disabled
0 = ME feature is enabled
1 = ME feature is disabled
56
RO
1b
Reserved
55:51
RO
0s
Reserved
50:49
RO
11b
Reserved
48
RO
0b
VT-d Disable (VTDD):
0 = Enable VT-d
1 = Disable VT-d
0 = Enable VT-d
1 = Disable VT-d
47
RO
0b
Reserved