Техническая Спецификация для Intel Xeon Wolfdale E3210 P4X-UPE3210-316-6M1333
Модели
P4X-UPE3210-316-6M1333
DRAM Controller Registers (D0:F0)
112
Datasheet
5.2.15
C0ECCERRLOG—Channel 0 ECC Error Log
B/D/F/Type:
0/0/0/MCHBAR
Address Offset: 280–287h
Default Value:
0000000000000000h
Access:
RO/P, RO
Size:
64 bits
This register is used to store the error status information in ECC enabled
configurations, along with the error syndrome and the rank/bank/row/column address
information of the address block of main memory of which an error (single bit or multi-
bit error) has occurred. Note that the address fields represent the address of the first
single or the first multiple bit error occurrence after the error flag bits in the ERRSTS
register have been cleared by software. A multiple bit error will overwrite a single bit
error. Once the error flag bits are set as a result of an error, this bit field is locked and
doesn't change as a result of a new error until the error flag is cleared by software.
Same is the case with error syndrome field, but the following priority needs to be
followed if more than one error occurs on one or more of the 4 QWs. MERR on QW0
MERR on QW1 MERR on QW2 MERR on QW3 CERR on QW0 CERR on QW1 CERR on
QW2 CERR on QW3
Bit
Access
Default
Value
Description
63:48
RO/P
0000h
Error Column Address (ERRCOL): Row address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
memory of which an error (single bit or multi-bit error) has occurred.
47:32
RO/P
0000h
Error Row Address (ERRROW): Row address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
memory of which an error (single bit or multi-bit error) has occurred.
31:29
RO/P
000b
Error Bank Address (ERRBANK): Rank address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
memory of which an error (single bit or multi-bit error) has occurred.
28:27
RO/P
00b
Error Rank Address (ERRRANK): Rank address of the address block of main
memory of which an error (single bit or multi-bit error) has occurred.
00 = rank 0 (DIMM0)
01 = rank 1 (DIMM0)
10 = rank 2 (DIMM1)
11 = rank 3 (DIMM1)
memory of which an error (single bit or multi-bit error) has occurred.
00 = rank 0 (DIMM0)
01 = rank 1 (DIMM0)
10 = rank 2 (DIMM1)
11 = rank 3 (DIMM1)
26:24
RO
0h
Reserved
23:16
RO/P
00h
Error Syndrome (ERRSYND): Syndrome that describes the set of bits
associated with the first failing quadword.
associated with the first failing quadword.
15:2
RO
0h
Reserved
1
RO/P
0b
Multiple Bit Error Status (MERRSTS): This bit is set when an uncorrectable
multiple-bit error occurs on a memory read data transfer. When this bit is set,
the address that caused the error and the error syndrome are also logged and
they are locked until this bit is cleared. This bit is cleared when it receives an
indication that the processor has cleared the corresponding bit in the ERRSTS
register.
multiple-bit error occurs on a memory read data transfer. When this bit is set,
the address that caused the error and the error syndrome are also logged and
they are locked until this bit is cleared. This bit is cleared when it receives an
indication that the processor has cleared the corresponding bit in the ERRSTS
register.
0
RO/P
0b
Correctable Error Status (CERRSTS): This bit is set when a correctable
single-bit error occurs on a memory read data transfer. When this bit is set, the
address that caused the error and the error syndrome are also logged and they
are locked to further single bit errors, until this bit is cleared. But, a multiple bit
error that occurs after this bit is set will over-write the address/error syndrome
info. This bit is cleared when it receives an indication that the processor has
cleared the corresponding bit in the ERRSTS register.
single-bit error occurs on a memory read data transfer. When this bit is set, the
address that caused the error and the error syndrome are also logged and they
are locked to further single bit errors, until this bit is cleared. But, a multiple bit
error that occurs after this bit is set will over-write the address/error syndrome
info. This bit is cleared when it receives an indication that the processor has
cleared the corresponding bit in the ERRSTS register.