Техническая Спецификация для Intel 2 Quad Q8400S BX80580Q8400S
Модели
BX80580Q8400S
Datasheet
19
Electrical Specifications
NOTES:
1.
1.
Each processor is programmed with a maximum valid voltage identification value (VID),
which is set at manufacturing and can not be altered. Individual maximum VID values are
calibrated during manufacturing such that two processors at the same frequency may have
different settings within the VID range. Note that this differs from the VID employed by the
processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep
which is set at manufacturing and can not be altered. Individual maximum VID values are
calibrated during manufacturing such that two processors at the same frequency may have
different settings within the VID range. Note that this differs from the VID employed by the
processor during a power management event (Thermal Monitor 2, Enhanced Intel
SpeedStep
®
technology, or Extended HALT State).
2.
Unless otherwise noted, all specifications in this table are based on estimates and
simulations or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
simulations or empirical data. These specifications will be updated with characterized data
from silicon measurements at a later date.
3.
These voltages are targets only. A variable voltage source should exist on systems in the
event that a different voltage is required. See
event that a different voltage is required. See
and
for more
information.
4.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE
lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.
lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe
capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the
probe should be less than 5 mm. Ensure external noise from the system is not coupled into
the oscilloscope probe.
5.
Refer to
, and
for the minimum, typical, and maximum
V
CC
allowed for a given current. The processor should not be subjected to any V
CC
and I
CC
combination wherein V
CC
exceeds V
CC_MAX
for a given current.
6.
I
CC_MAX
specification is based on V
CC_
MAX
loadline. Refer to
for details.
7.
V
TT
must be provided via a separate voltage source and not be connected to V
CC
. This
specification is measured at the land.
8.
Baseboard bandwidth is limited to 20 MHz.
9.
This is the maximum total current drawn from the V
TT
plane by only the processor. This
specification does not include the current coming from on-board termination (R
TT
),
through the signal line. Refer to the Voltage Regulator Design Guide to determine the total
I
I
TT
drawn by the system. This parameter is based on design characterization and is not
tested.
10.
Adherence to the voltage specifications for the processor are required to ensure reliable
processor operation.
processor operation.
Table 5.
Intel
®
Core™2 Duo Processor E8000 Series V
CC
Static and Transient
Tolerance
I
CC
(A)
Voltage Deviation from VID Setting (V)
1, 2, 3, 4
Maximum Voltage
1.40 mΩ
Typical Voltage
1.48 mΩ
Minimum Voltage
1.55 mΩ
0
0.000
-0.019
-0.038
5
-0.007
-0.026
-0.046
10
-0.014
-0.034
-0.054
15
-0.021
-0.041
-0.061
20
-0.028
-0.049
-0.069
25
-0.035
-0.056
-0.077
30
-0.042
-0.063
-0.085
35
-0.049
-0.071
-0.092
40
-0.056
-0.078
-0.100
45
-0.063
-0.085
-0.108
50
-0.070
-0.093
-0.116
55
-0.077
-0.100
-0.123
60
-0.084
-0.108
-0.131