Техническая Спецификация для Intel Xeon E7430 AD80583QH046003
Модели
AD80583QH046003
Electrical Specifications
40
Intel® Xeon® Processor 7400 Series Datasheet
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Not 100% tested. Specified by design characterization.
3.
This specification is based on the capabilities of the ITP debug port, not on processor silicon.
4.
Referenced to the rising edge of TCK.
5.
Referenced to the falling edge of TCK.
6.
TRST# must be held asserted for 2 TCK periods to be guaranteed that it is recognized by the processor.
7.
Specification for a minimum swing defined between TAP V
t-
to V
t+
. This assumes a minimum edge rate of
0.5 V/ns.
8.
It is recommended that TMS be asserted while TRST# is being deasserted.
.
Notes:
1.
See Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 11.0 Design
Guidelines for addition information.
2.
Platform support for VID transitions is required for the processor to operate within specifications.
Table 2-24. TAP Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1, 2, 8
T55: TCK Period
30
ns
3
T56: TDI, TMS Setup Time
7.5
ns
4,7
T57: TDI, TMS Hold Time
7.5
ns
4,7
T58: TDO Clock to Output Delay
0
7.5
ns
5
T59: TRST# Assert Time
2
T
TCK
6
Table 2-25. VID Signal Group AC Specifications
T # Parameter
Min
Max
Unit
Figure
Notes
1, 2
T80: VID Step Time
5
µs
T81: VID Dwell Time
50
µs
T82: VID Down Transition to Valid V
CC
(min)
0
µs
T83: VID Up Transition to Valid V
CC
(min)
50
µs
T84: VID Down Transition to Valid V
CC
(max)
50
µs
T85: VID Up Transition to Valid V
CC
(max)
0
µs
Table 2-26. SMBus Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1, 2
Notes:
1.
These parameters are based on design characterization and are not tested.
2.
All AC timings for the SMBus signals are referenced at V
IL_MAX
or V
IL_MIN
and measured at the processor
pins. Refer to
.
T90: SM_CLK Frequency
10
100
KHz
T91: SM_CLK Period
10
100
µs
T92: SM_CLK High Time
4.0
N/A
µs
T93: SM_CLK Low Time
4.7
N/A
µs
T94: SMBus Rise Time
0.02
1.0
µs
3
T95: SMBus Fall Time
0.02
0.3
µs
T96: SMBus Output Valid Delay
0.1
4.5
µs
T97: SMBus Input Setup Time
250
N/A
ns
T98: SMBus Input Hold Time
300
N/A
ns
T99: Bus Free Time
4.7
N/A
µs
4,
5
T100: Hold Time after Repeated Start Condition
4.0
N/A
µs
T101: Repeated Start Condition Setup Time
4.7
N/A
µs
T102: Stop Condition Setup Time
4.0
N/A
µs