Справочник Пользователя для Intel Xeon L5506 P4X-DPL5506-213-4M480
Модели
P4X-DPL5506-213-4M480
Signal Definitions
88
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
§
VTT_VID[4:2]
O
VTT_VID[4:2] is used to support automatic selection of power supply voltages
(V
TT
). The voltage supply for this signal must be valid before the VR can supply
V
TT
to the processor. Conversely, the VR output must be disabled until the
voltage supply for the VID signal become valid. The VID signal is needed to
support the processor voltage specification variations. The VR must supply the
voltage that is requested by the signal.
V
TTA
I
Power for the analog portion of the Intel QuickPath Interconnect and Shared
Cache.
V
TTD
I
Power for the digital portion of the Intel QuickPath Interconnect and Shared
Cache.
VDDPWRGOOD
I
VDDPWRGOOD is an input that indicates the Vddq power supply is good. The
processor requires this signal to be a clean indication that the Vddq power supply
is stable and within their specifications. "Clean" implies that the signal will
remain low (capable of sinking leakage current), without glitches, from the time
that the Vddq supply is turned on until it come within specification. The signals
must then transition monotonically to a high state.
The PwrGood signal must be supplied to the processor, This signal is used to
The PwrGood signal must be supplied to the processor, This signal is used to
protect internal circuits against voltage sequencing issues.
VID[7:6]
VID[5:3]/CSC[2:0]
VID[2:0]/MSID[2:0]
VID[5:3]/CSC[2:0]
VID[2:0]/MSID[2:0]
I/O
VID[7:0] (Voltage ID) are output signals that are used to support automatic
selection of power supply voltages (V
CC
). The voltage supply for these signals
must be valid before the VR can supply V
CC
to the processor. Conversely, the VR
output must be disabled until the voltage supply for the VID signals become
valid. The VID signals are needed to support the processor voltage specification
variations. The VR must supply the voltage that is requested by the signals, or
disable itself.
VID7 and VID6 should be tied separately to V
VID7 and VID6 should be tied separately to V
SS
via 1kOhm resistors during reset
(this value is latched on the rising edge of VTTPWRGOOD).
MSID[2:0] - Market Segment ID, or MSID are provided to indicate the Market
MSID[2:0] - Market Segment ID, or MSID are provided to indicate the Market
Segment for the processor and may be used for future processor compatibility or
for keying. In addition, MSID protects the platform by preventing a higher power
processor from booting in a platform designed for lower power processors. This
value is latched from the platform in to the CPU, on the rising edge of
VTTPWRGOOD, during the cold boot power up sequence.
CSC[2:0] - Current Sense Configuration bits are output signals for ISENSE gain
CSC[2:0] - Current Sense Configuration bits are output signals for ISENSE gain
setting. This value is latched on the rising edge of VTTPWRGOOD.
2
V
TTD_SENSE
V
SS_SENSE_VTT
O
O
O
V
TTD_SENSE
and V
SS_SENSE_VTT
provide an isolated, low impedance connection to
the processor power and ground. They can used to sense or measure power near
the silicon.
VTTPWRGOOD
I
The processor requires this input signal to be a clean indication that the VTT
power supply is stable and within their specifications. 'Clean' implies that the
signal will remain low (capable of sinking leakage current), without glitches,
from the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high state. to
determine that the VTT voltage is stable and within specification. Note it is not
valid for VTTPWRGOOD to be deasserted while VCCPWRGOOD is asserted.
V
SS
The processor ground.
Notes:
1. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.
2. VID[7:0] is an Input only during Power On Configuration. It is an Output signal during normal operation.
Table 5-1.
Signal Definitions (Sheet 4 of 4)
Name
Type
Description
Notes