Техническая Спецификация для Intel Pentium III BX80525U550512E

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Datasheet
Thermal Specifications and Design Considerations
For S.E.C.C. packaged processors, the extended thermal plate is the attach location for all thermal 
solutions. The maximum and minimum extended thermal plate temperatures are specified in 
For S.E.C.C.2 packaged processors, thermal solutions attach to the processor by 
connecting through the substrate to the cover. The maximum and minimum temperatures of the 
pertinent locations are specified in 
. A thermal solution should be designed to ensure the 
temperature of the specified locations never exceeds these temperatures.
The total processor power is a result of heat dissipated by the processor core and L2 cache. The 
overall system chassis thermal design must comprehend the entire processor power. In S.E.C.C. 
packaged processors, the extended thermal plate power is a component of this power, and is 
primarily composed of the processor core and the L2 cache dissipating heat through the extended 
thermal plate. The heatsink need only be designed to dissipate the extended thermal plate power. 
See 
 for current Pentium III processor S.E.C.C. thermal design specifications.
No extended thermal plate exists for S.E.C.C.2 packaged processors, so thermal solutions have to 
attach directly to the processor core package. The total processor power dissipated by an S.E.C.C.2 
processor is a combination of heat dissipated by both the processor core and L2 cache. Pentium III 
processors that use a “Discrete” L2 cache have a separate T
CASE
 specification (
) for the 
surface mounted BSRAM components on the substrate. T
JUNCTION
 encompasses the L2 cache for 
processors that utilize the “Advanced Transfer Cache”, therefore no separate cache measurement is 
required.
Specifics on how to measure these specifications are outlined in AP-905, Intel
®
 Pentium
®
 III 
Processor Thermal Design Guidelines (Document Number 245087).
Figure 20. Processor Functional Die Layout (CPUID=0686h)
Cache Area
0.04 in
2
0.337”
0.275”
0.146”
0.414”
Core Area
0.10 in
2
Die Area
0.14 in
2
Die Area = 0.90 cm
2
Cache Area = 0.26 cm
2
Core Area = 0.64 cm
2
Figure 21. Processor Functional Die Layout (up to CPUID=0683h)
Cache Area
0.05 in
2
0.362”
0.292”
0.170”
0.448”
Core Area
0.11 in
2
Die Area
0.16 in
2
Die Area = 1.05 cm
2
Cache Area = 0.32 cm
2
Core Area = 0.73 cm
2