Справочник Пользователя для Intel B940 FF8062700847801
Модели
FF8062700847801
Datasheet, Volume 1
57
Signal Description
COMP2
Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
for the termination requirement.
I
Analog
COMP3
Impedance compensation must be terminated on the
system board using a precision resistor. Refer to
for the termination requirement.
I
Analog
FC_x
Future Compatibility (FC) signals are signals that are
available for compatibility with other processors. A test
point may be placed on the board for these lands.
PM_EXT_TS#[1:0]
External Thermal Sensor Input: If the system
temperature reaches a dangerously high value, this
signal can be used to trigger the start of system
memory throttling.
I
CMOS
PM_SYNC
Power Management Sync: A sideband signal to
communicate power management status from the
platform to the processor.
I
CMOS
RESET_OBS#
This signal is an indication of the processor being reset.
O
Asynch
CMOS
RSTIN#
Reset In: When asserted, this signal will asynchronously
reset the processor logic. This signal is connected to the
PLTRST# output of the PCH.
I
CMOS
RSVD
RESERVED. Must be left unconnected on the board.
Intel does not recommend a test point on the board for
this land.
RSVD_NCTF
RESERVED/Non-Critical to Function: Pin for package
mechanical reliability. A test point may be placed on the
board for this land.
RSVD_TP
RESERVED-Test Point. A test point may be placed on the
board for this land.
SM_DRAMRST#
DDR3 DRAM Reset: Reset signal from processor to
DRAM devices. One common to all channels.
O
DDR3
Table 6-5.
Reset and Miscellaneous Signals (Sheet 2 of 2)
Signal Name
Description
Direction
Type