Справочник Пользователя для Elixir M2U25664DS88B3G-5T

  

Preliminary

 

 

Symbol 

Type 

Polarity 

Function 

CK0, CK1, CK2, 

CK0, CK1, CK2 

(SSTL) 

Cross 

point 

The system clock inputs. All address and command lines are sampled on the cross point of 
the rising edge of CK and falling edge of CK. A Delay Locked Loop (DLL) circuit is driven 
from the clock inputs and output timing for read operations is synchronized to the input 
clock. 

CKE0, CKE1 

(SSTL) 

Active 

High 

Activates the DDR SDRAM CK signal when high and deactivates the CK signal when low. 
By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh 
mode. 

S0, S1 

(SSTL) 

Active 

Low 

Enables the associated DDR SDRAM command decoder when low and disables the 
command decoder when high. When the command decoder is disabled, new commands are 
ignored but previous operations continue. Physical Bank 0 is selected by S0; Bank 1 is 
selected by S1. 

RAS, CAS, WE 

(SSTL) 

Active 

Low 

When sampled at the positive rising edge of the clock, RAS, CAS, WE define the operation to 
be executed by the SDRAM. 

V

REF

 Supply 

 

Reference voltage for SSTL-2 inputs 

V

DDQ

  

Supply 

 

Isolated power supply for the DDR SDRAM output buffers to provide improved noise 
immunity 

BA0, BA1 

(SSTL) - Selects which SDRAM bank is to be active. 

A0 - A9 

A10/AP 

A11, A12 

(SSTL) - 

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when 
sampled at the rising clock edge. 
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) 
when sampled at the rising clock edge. In addition to the column address, AP is used to 
invoke auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high, 
auto-precharge is selected and BA0/BA1 defines the bank to be precharged. If AP is low, 
auto-precharge is disabled. 
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control 
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the 
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge.

DQ0 - DQ63 

(SSTL) - 

Data and Check Bit input/output pins operate in the same manner as on conventional 
DRAMs. 

DQS0 - DQS7, 

DQS9 – DQS16 

(SSTL) 

Active 

High 

Data strobes: Output with read data, input with write data. Edge aligned with read data, 
centered on write data. Used to capture write data. 

CB0 – CB7 

(SSTL) 

 

Data Check Bit Input/Output pins.  Used on ECC modules and is not used on x64 modules.

DM0 – DM8 

Input 

Active 

High 

The data write masks, associated with one data byte. In Write mode, DM operates as a byte
mask by allowing input data to be written if it is low but blocks the write operation if it is high. 
In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is 
not used on x64 modules. 

V

DD

, V

SS

 Supply 

 

Power and ground for the DDR SDRAM input buffers and core logic 

SA0 – SA2  

Address inputs. Connected to either V

DD

 or V

SS

on the system board to configure the Serial 

Presence Detect EEPROM address. 

SDA  

This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor 
must be connected from the SDA bus line to V DD to act as a pull-up. 

SCL  

This signal is used to clock data into and out of the SPD EEPROM. A resistor may be 
connected from the SCL bus time to V DD to act as a pull-up. 

V

DDSPD

Supply 

Serial EEPROM positive power supply.