Справочник Пользователя для Intel D525 AU80610006225AA
Модели
AU80610006225AA
Introduction
12
Datasheet
Execute Disable Bit
The Execute Disable bit allows memory to be marked as executable or
non-executable, when combined with a supporting operating system.
If code attempts to run in non-executable memory the processor
raises an error to the operating system. This feature can prevent some
classes of viruses or worms that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. See the
Intel
non-executable, when combined with a supporting operating system.
If code attempts to run in non-executable memory the processor
raises an error to the operating system. This feature can prevent some
classes of viruses or worms that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. See the
Intel
®
64 and IA-32 Architectures Software Developer's Manuals for
more detailed information.
Micro-FBGA
Micro Flip Chip Ball Grid Array
(G)MCH
Legacy component - Graphics Memory Controller Hub. Platforms
designed for the Intel Atom Processor D400 and D500 Series do not
use an (G)MCH.
designed for the Intel Atom Processor D400 and D500 Series do not
use an (G)MCH.
GPU
Graphics Processing Unit
ICH
The legacy I/O Controller Hub component that contains the main PCI
interface, LPC interface, USB2, Serial ATA, and other I/O functions. It
communicates with the legacy (G)MCH over a proprietary interconnect
called DMI. Platforms designed for the Intel® Atom™ Processor D400
and D500 Series do not use an ICH.
interface, LPC interface, USB2, Serial ATA, and other I/O functions. It
communicates with the legacy (G)MCH over a proprietary interconnect
called DMI. Platforms designed for the Intel® Atom™ Processor D400
and D500 Series do not use an ICH.
IMC
Integrated Memory Controller
Intel
®
64 Technology
64-bit memory extensions to the IA-32 architecture.
LCD
Liquid Crystal Display
LLC
Last Level Cache. The LLC is the shared cache amongst all processor
execution cores
execution cores
LVDS
Low Voltage Differential Signaling
A high speed, low power data transmission standard used for display
connections to LCD panels.
A high speed, low power data transmission standard used for display
connections to LCD panels.
MCP
Multi-Chip Package
NCTF
Non-Critical to Function: NCTF locations are typically redundant
ground or non-critical reserved, so the loss of the solder joint
continuity at end of life conditions will not affect the overall product
functionality.
ground or non-critical reserved, so the loss of the solder joint
continuity at end of life conditions will not affect the overall product
functionality.
Processor
The 64-bit, single-core or multi-core component (package)
Processor Core
The term “processor core” refers to Si die itself which can contain
multiple execution cores. Each execution core has an instruction
cache, data cache, and 256-KB L2 cache. All execution cores share the
L3 cache.
multiple execution cores. Each execution core has an instruction
cache, data cache, and 256-KB L2 cache. All execution cores share the
L3 cache.
Rank
A unit of DRAM corresponding four to eight devices in parallel, ignoring
ECC. These devices are usually, but not always, mounted on a single
side of a SO-DIMM.
ECC. These devices are usually, but not always, mounted on a single
side of a SO-DIMM.
SCI
System Control Interrupt. Used in ACPI protocol.
SMT
Simultaneous Multi-Threading
Term
Description