Справочник Пользователя для Intel D425 AU80610006252AA
Модели
AU80610006252AA
Processor Configuration Registers
40
Datasheet
Bit Access Default
Value
RST/
PWR
Description
NOTE: This register is locked and becomes
Read Only when the D_LCK bit in the
SMRAM register is set.
SMRAM register is set.
BIOS Requirement: BIOS must not set this
field to 000 if IVD (bit 1 of this register) is 0.
field to 000 if IVD (bit 1 of this register) is 0.
3:2 RO 00b Core
Reserved ()
1 RW/L 0b Core
IGD VGA Disable (IVD):
0: Enable. Device 2 (IGD) claims VGA memory
and IO cycles, the Sub-Class Code within
Device 2 Class Code register is 00.
1: Disable. Device 2 (IGD) does not claim VGA
cycles (Mem and IO), and the Sub- Class Code
field within Device 2 function 0 Class Code
register is 80.
BIOS Requirement: BIOS must not set this bit
to 0 if the GMS field (bits 6:4 of this register)
pre-allocates no memory. This bit MUST be
set to 1 if Device 2 is disabled.
0: Enable. Device 2 (IGD) claims VGA memory
and IO cycles, the Sub-Class Code within
Device 2 Class Code register is 00.
1: Disable. Device 2 (IGD) does not claim VGA
cycles (Mem and IO), and the Sub- Class Code
field within Device 2 function 0 Class Code
register is 80.
BIOS Requirement: BIOS must not set this bit
to 0 if the GMS field (bits 6:4 of this register)
pre-allocates no memory. This bit MUST be
set to 1 if Device 2 is disabled.
0 RO 0b Core
Reserved ()