Справочник Пользователя для Intel D425 AU80610006252AA
Модели
AU80610006252AA
Processor Configuration Registers
Datasheet
49
1.5.22
PAM4 - Programmable Attribute Map 4
B/D/F/Type: 0/0/0/PCI
Address Offset:
94h
Default Value:
00h
Access:
RO; RW/L;
Size: 8
bits
This register controls the read, write, and shadowing attributes of the BIOS areas
from 0D8000h- 0DFFFFh.
from 0D8000h- 0DFFFFh.
Bit Acces
s
Defau
lt
Value
RST/
PWR
Description
7:6 RO 00b Core
Reserved ()
5:4 RW/L 00b Core
0DC000-0DFFFF Attribute (HIENABLE):
This field controls the steering of read and write
cycles that address the BIOS area from 0DC000 to
0DFFFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads
are serviced by DMI.
11: Normal DRAM Operation: All reads and writes
are serviced by DRAM.
This field controls the steering of read and write
cycles that address the BIOS area from 0DC000 to
0DFFFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads
are serviced by DMI.
11: Normal DRAM Operation: All reads and writes
are serviced by DRAM.
3:2 RO 00b Core
Reserved ()
1:0 RW/L 00b Core
0D8000-0DBFFF Attribute (LOENABLE):
This field controls the steering of read and write
cycles that address the BIOS area from 0D8000 to
0DBFFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads
are serviced by DMI.
11: Normal DRAM Operation: All reads and writes
are serviced by DRAM.
This field controls the steering of read and write
cycles that address the BIOS area from 0D8000 to
0DBFFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All
writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads
are serviced by DMI.
11: Normal DRAM Operation: All reads and writes
are serviced by DRAM.