Справочник Пользователя для Intel D425 AU80610006252AA

Datasheet 

 59 

B/D/F/Type: 0/0/0/PCI 

Address Offset: 

AC-AFh 

Default Value: 

00000000h 

Access: 

 RW/L; RO; 

Size: 32 

bits 

This register contains the base address of TSEG DRAM memory. BIOS determines the 
base of TSEG memory by subtracting the TSEG size (PCI Device 0 offset 9E bits 
02:01) from graphics GTT stolen base (PCI Device 0 offset A8 bits 31:20).  

Once D_LCK has been set, these bits becomes read only. 

 

 

31:20 RW/L  000h  Core 

TESG Memory base (TSEGMB):  
This register contains bits 31 to 20 of the base address of 
TSEG DRAM memory. BIOS determines the base of TSEG 
memory by subtracting the TSEG size (PCI Device 0 offset 
9E bits 02:01) from graphics GTT stolen base (PCI Device 
0 offset A8 bits 31:20).  

Once D_LCK has been set, these bits become read only.

 

19:0 RO 00000h 

Core 

B/D/F/Type: 0/0/0/PCI 

Address Offset: 

B0-B1h 

Default Value: 

0010h 

Access: 

 RW/L; RO; 

Size: 16 

bits 

This 16 bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics Memory 
and Graphics Stolen Memory are within the DRAM space defined. From the top, CPU 

Uncore optionally claims 1 to 64MBs of DRAM for internal graphics if enabled 1, 2MB 
of DRAM for GTT Graphics Stolen Memory (if enabled) and 1, 2, or 8 MB of DRAM for 

TSEG if enabled. 

Programming Example :  

⎯  C1DRB3 is set to 4GB 
⎯  TSEG is enabled and TSEG size is set to 1MB 
⎯  Internal Graphics is enabled and Graphics Mode Select set to 32MB 
⎯  GTT Graphics Stolen Memory Size set to 2MB 
⎯  BIOS knows the OS requires 1G of PCI space.