Справочник Пользователя для Intel D425 AU80610006252AA
Модели
AU80610006252AA
Processor Configuration Registers
Datasheet
95
1.7.16
DMILE2A - DMI Link Entry 2 Address
B/D/F/Type: 0/0/0/DMIBAR
Address Offset:
68-6Fh
Default Value:
0000000000000000h
Access:
RO; RWO;
Size: 64
bits
Second part of a Link Entry which declares an internal link to another Root Complex
Element.
Element.
Bit Access Default
Value
RST/
PWR
Description
63:36 RO 0000000h
Core
Reserved ():
Reserved for Link Address high order bits.
Reserved for Link Address high order bits.
35:12 RWO 000000h Core
Link Address (LA):
Memory mapped base address of the RCRB that
is the target element (Egress Port) for this link
entry.
Memory mapped base address of the RCRB that
is the target element (Egress Port) for this link
entry.
11:0 RO 000h Core
Reserved ()
1.7.17
DMIRCILCECH - DMI Root Complex Internal Link Control
B/D/F/Type: 0/0/0/DMIBAR
Address Offset:
80-83h
Default Value:
00010006h
Access:
RO;
Size: 32
bits
This capability contains controls for the Root Complex Internal Link known as DMI.
Bit Access Default
Value
RST/
PWR
Description
31:20 RO 000h Core
Pointer to Next Capability (PNC):
This value terminates the PCI Express
extended capabilities list associated with this
RCRB.
This value terminates the PCI Express
extended capabilities list associated with this
RCRB.
19:16 RO
1h Core
Link Declaration Capability Version (LDCV):
Hardwired to 1 to indicate compliances with
the 1.1 version of the PCI Express specification.
Hardwired to 1 to indicate compliances with
the 1.1 version of the PCI Express specification.
15:0 RO 0006h Core
Extended Capability ID (ECID):
Value of 0006 h identifies this linked list item
(capability structure) as being for PCI Express
Internal Link Control Capability.
Value of 0006 h identifies this linked list item
(capability structure) as being for PCI Express
Internal Link Control Capability.