Справочник Пользователя для Intel D425 AU80610006252AA
Модели
AU80610006252AA
Processor Configuration Registers
98
Datasheet
1.7.20
DMILSTS - DMI Link Status
B/D/F/Type: 0/0/0/DMIBAR
Address Offset:
8A-8Bh
Default Value:
0001h
Access:
RO;
Size: 16
bits
Indicates DMI status.
Bit Acces
s
Defau
lt
Value
RST/
PWR
Description
15:10 RO 00h Core
Reserved ()
9:4 RO 00h Core
Negotiated Width (NWID):
Indicates negotiated link width. This field is valid only
when the link is in the L0, L0s, or L1 states (after link
width negotiation is successfully completed).
00h: Reserved
01h: X1
02h: X2
04h: X4
All other encodings are reserved.
Indicates negotiated link width. This field is valid only
when the link is in the L0, L0s, or L1 states (after link
width negotiation is successfully completed).
00h: Reserved
01h: X1
02h: X2
04h: X4
All other encodings are reserved.
3:0 RO 1h Core
Negotiated Speed (NSPD):
Indicates negotiated link speed.
1h: 2.5 Gb/s
All other encodings are reserved.
Indicates negotiated link speed.
1h: 2.5 Gb/s
All other encodings are reserved.
1.8
EPBAR
Register
Name
Register
Symbol
Register
Start
Register
End
Default Value
Access
EP Element
Self
Description
Self
Description
EPESD 44 47 00000201h
RO;
RWO;
EP Link Entry 1
Description
Description
EPLE1D 50 53 01000000h
RO;
RWO;
EP Link Entry 1
Address
Address
EPLE1A 58 5F 00000000000000
00h
RO; RWO;
EP Link Entry 2
Description
Description
EPLE2D 60 63 02000002h
RO;
RWO;
EP Link Entry 2
Address
Address
EPLE2A 68 6F 00000000000080
00h
RO;