Справочник Пользователя для Intel Xeon L3406 CM80616005010AA

82

Datasheet, Volume 2

27

RWS

0

System Interrupt Only on Link BW/Management Status
This bit, when set, will disable generating MSI interrupt on link bandwidth 

(speed and/or width) and management changes, even if MSI is enabled 

that is, will disable generating MSI when LNKSTS Bits 15 and 14 are set.

26

RW

0

Disable EOI Broadcast to this PCI Express link
When set, EOI message will not be broadcast down this PCI Express link. 

When clear, the port is a valid target for EOI broadcast.

25

RW

0

Peer-to-Peer Memory Write Disable
When set, peer-to-peer memory writes are master aborted otherwise they 

are allowed to progress per the peer-to-peer decoding rules.

24

RV

1

23

RW

0

Phold Disable
When set, the IIO responds with unsupported request on receiving 

assert_phold message from PCH and results in generating a fatal error.

22:10

RV

--

9

RV

0

8:7

RW

0

PME_TO_ACK Time-out Control
This field sets the time-out value for receiving a PME_TO_ACK message 

after a PME_TURN_OFF message has been transmitted. This field has 

meaning only if bit 6 is set to a 0b.
00 = 1 ms
01 = 10 ms
10 = 50 ms
11 = test mode

6

RW

0

Disable Time-out for Receiving PME_TO_ACK
When set, IIO disables the time-out to receiving the PME_TO_ACK.

5

RW

0

Send PME_TURN_OFF Message
When this bit is written with a 1, IIO sends a PME_TURN_OFF message to 

the PCI Express link. Hardware clears this bit when the message has been 

sent on the link.

4

RW

0

When set, the PCI Express errors do not trigger an MSI interrupt, 

regardless of the whether MSI is enabled or not. 
When this bit is cleared, PCI Express errors are reported using MSI and/or 

NMI/SMI/MCA. When this bit is clear and if MSI enable bit in the MSICTRL 

register is set, then an MSI interrupt is generated for PCI Express errors. 

When this bit is clear, and ‘System Error on Fatal Error Enable’ bit in 

 is set, 

then NMI/SMI/MCA is (also) generated for a PCI Express fatal error. 

Similar behavior for non-fatal and corrected errors.

3

RW

0

2

RW

0

Enable ACPI Mode for PM
When set, all PM events at the PCI Express port are handled using 

_PMEGPE messages to the PCH, and no MSI interrupts are ever generated 

for PM events at the root port (regardless of whether MSI is enabled at the 

root port or not). When clear, _PMEGPE message generation for PM events 

is disabled and OS can choose to generate MSI interrupts for delivering PM 

events by setting the MSI enable bit in root ports. This bit does not apply 

to the DMI ports.
Clearing this bit (from being 1) schedules a Deassert_PMEGPE event on 

behalf of the root port, provided there was any previous Assert_PMEGPE 

message that was sent without an associated Deassert message.