Справочник Пользователя для Intel 2 Duo T7800 LE80537GG0644M

Datasheet

31

NOTES:
1.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at 
manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing 
in such a way that two processors at the same frequency may have different settings within the VID range. 
Note that this differs from the VID employed by the processor during a power management event (Intel 
Thermal Monitor 2, Enhanced Intel SpeedStep Technology, or Extended Halt State). 

2.

The voltage specifications are assumed to be measured across V

CC_SENSE

 and V

SS_SENSE 

pins at socket with 

a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-mΩ minimum impedance. 
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from 
the system is not coupled in the scope probe. 

3.

Specified at 100°C Tj. 

4.

Specified at the nominal V

CC

.

5.

800-MHz FSB supported

6.

Instantaneous current I

CC_CORE_INST

 of 55 A has to be sustained for short time (t

INST

) of 10 µs. Average 

current is less than maximum specified I

CCDES

. VR OCP threshold should be high enough to support current 

levels described herein.

7.

Measured at the bulk capacitors on the motherboard.

8.

The maximum delta between Intel Enhanced Deeper Sleep and LFM on the processor is lesser than or 
equal to 350 mV. 

9.

Based on simulations and averaged over the duration of any change in current. Specified by design/
characterization at nominal V

CC

. Not 100% tested.

10.

This is a power-up peak current specification, which is applicable when V

CCP

 is high and V

CC_CORE

 is low.

11.

This is a steady-state I

CC

 current specification, which is applicable when both V

CCP

 and V

CC_CORE

 are high.

12.

Processor I

CC

 requirements in Intel Dynamic Acceleration Technology mode is lesser than I

CC

 in HFM.

13.

4-M L2 cache.

14.

2-M L2 cache.

I

DSLP

I

CC

 Deep Sleep

HFM
SuperLFM

25.0
16.0

A

3,  4,  12

I

DPRSLP

I

CC

 Deeper Sleep 

11.5

A

3, 4

I

DC4

I

CC

 Intel Enhanced Deeper Sleep

9.4

A

3, 4

dI

CC/DT

V

CC 

Power Supply Current Slew Rate at 

Processor Package Pin

600

A/µs

7, 9

I

CCA

I

CC

 for V

CCA 

Supply

130

mA

I

CCP

I

CC

 for V

CCP 

Supply before V

CC

 Stable

I

CC

 for V

CCP 

Supply after V

CC

 Stable

4.5
2.5

A
A

10
11