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Datasheet

If a processor load-based Enhanced Intel SpeedStep Technology/P-state transition 

(through MSR write) is initiated while the Adaptive Thermal Monitor is active, there are 

two possible outcomes:

• If the P-state target frequency is higher than the processor core optimized target 

frequency, the p-state transition will be deferred until the thermal event has been 

completed.

• If the P-state target frequency is lower than the processor core optimized target 

frequency, the processor will transition to the P-state operating point.

If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor 

event, the Adaptive Thermal Monitor will utilize clock modulation. Clock modulation is 

done by alternately turning the clocks off and on at a duty cycle (ratio between clock 

“on” time and total time) specific to the processor. The duty cycle is factory configured 

to 37.5% on and 62.5% off and cannot be modified. The period of the duty cycle is 

configured to 32 microseconds when the TCC is active. Cycle times are independent of 

processor frequency. A small amount of hysteresis has been included to prevent 

excessive clock modulation when the processor temperature is near its maximum 

operating temperature. Once the temperature has dropped below the maximum 

operating temperature, and the hysteresis timer has expired, the TCC goes inactive and 

clock modulation ceases. Clock modulation is automatically engaged as part of the TCC 

activation when the frequency/VID targets are at their minimum settings. Processor 

performance will be decreased by the same amount as the duty cycle when clock 

modulation is active. Snooping and interrupt processing are performed in the normal 

manner while the TCC is active.

Each processor execution core has an on-die Digital Thermal Sensor (DTS) which 

detects the core’s instantaneous temperature. The DTS is the preferred method of 

monitoring processor die temperature because 

• It is located near the hottest portions of the die.
• It can accurately track the die temperature and ensure that the Adaptive Thermal 

Monitor is not excessively activated. 

Temperature values from the DTS can be retrieved through

• A software interface via processor Model Specific Register (MSR). 
• A processor hardware interface as described in 

, must be enabled for the product to remain within specification.

When temperature is retrieved by processor MSR, it is the instantaneous temperature 

of the given core. When temperature is retrieved via PECI, it is the average 

temperature of each execution core’s DTS over a programmable window (default 

window of 256 ms.) Intel recommends using the PECI output reading for fan speed or 

other platform thermal control.

Code execution is halted in C1-C6. Therefore temperature cannot be read via the 

processor MSR without bringing a core back into C0. However, temperature can still be 

monitored through PECI in lower C-states. 

Unlike traditional thermal devices, the DTS outputs a temperature relative to the 

maximum supported operating temperature of the processor (T

j,max

). It is the 

responsibility of software to convert the relative temperature to an absolute 

temperature. The absolute reference temperature is readable in an MSR. The 

temperature returned by the DTS is an implied negative integer indicating the relative 

offset from T

j,max

. The DTS does not report temperatures greater than T

j,max

.