Техническая Спецификация для Intel LF80550KG0888M
Introduction
14
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Note:
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset
of the I
2
C bus/protocol and was developed by Intel. Implementations of the I
2
C
bus/protocol or the SMBus bus/protocol may require licenses from various entities,
including Philips Electronics N.V. and North American Philips Corporation.
• Storage Conditions — Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor pins should not be connected
to any supply voltages, have any I/Os biased, or receive any clocks.
exposed to free air. Under these conditions, processor pins should not be connected
to any supply voltages, have any I/Os biased, or receive any clocks.
• Symmetric Agent - A symmetric agent is a processor which shares the same I/O
subsystem and memory array, and runs the same operating system as another
processor in a system. Systems using symmetric agents are known as Symmetric
MultiProcessing (SMP) systems. Dual-Core Intel Xeon processor 7100 series
processors should only be used in SMP systems which have two or fewer symmetric
agents per front side bus.
processor in a system. Systems using symmetric agents are known as Symmetric
MultiProcessing (SMP) systems. Dual-Core Intel Xeon processor 7100 series
processors should only be used in SMP systems which have two or fewer symmetric
agents per front side bus.
• Dual-Core Intel Xeon processor 7100 series — The entire product, including
processor core substrate and integrated heat spreader (IHS).
1.2
References
Material and concepts available in the following documents may be beneficial when
reading this document:
reading this document:
Document
Intel Order Number
Notes
AP-485, Intel® Processor Identification and the CPUID Instruction
241618
4
IA-32 Intel® Architecture Software Developer's Manual
• Volume 1: Basic Architecture
• Volume 2A: Instruction Set Reference, A-M
• Volume 2B: Instruction Set Reference, N-Z
• Volume 3A: System Programming Guide
• Volume 3B: System Programming Guide
• Volume 2A: Instruction Set Reference, A-M
• Volume 2B: Instruction Set Reference, N-Z
• Volume 3A: System Programming Guide
• Volume 3B: System Programming Guide
253665
253666
253667
253668
253669
253666
253667
253668
253669
4
IA-32 Intel® Architecture Software Developer's Manual Documentation
Changes
252046
4
IA-32 Intel® Architecture Optimization Reference Manual
248966
4
Intel® Extended Memory 64 Technology Software Developer’s Manual
• Volume 1
• Volume 2
• Volume 2
300834
300835
300835
4
IA-32 Intel® Architecture and Intel® Extended Memory 64 Technology
Software Developer's Manual Documentation Changes
252046
4
Dual-Core Intel® Xeon® Processor 7100 Series Specification Update
314554
4
Dual-Core Intel® Xeon® Processor 7100 Series Boundary Scan
Descriptive Language (BSDL) Files
4
Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical
Design Guidelines
314555
4
Dual-Core Intel® Xeon® Processor 7100 Series Thermal Test Vehicle
and Cooling Solution Thermal Models
4
64-bit Intel® Xeon® Processor MP with up to 8MB L3 Cache Cooling
Solution Mechanical Models
1
64-bit Intel® Xeon® Processor MP with up to 8MB L3 Cache Mechanical
Models
2
Cedar Mill Processor Family BIOS Writer’s Guide (BWG)
3
eXtended Debug Port: Debug Port Design Guide for MP Platforms
3
mPGA604 Socket Design Guidelines
254239
4