Справочник Пользователя для Intel Itanium 9310 LW80603003243AA
Модели
LW80603003243AA
Intel Itanium Processor 9300 Series Signal Definitions
120
Intel
®
Itanium
®
Processor 9300 Series Datasheet
§
VRPWRGD
I /O
This signal is open drain/collector driven by Ararat Voltage Regulator into a pad at
the top of the processor package and out through a pin at the bottom of the
processor package. When pulled up (active high state), it indicates that the supply
voltages to VCCCORE, VCCUNCORE, and VCCCACHE are stable within their voltage
specification, and indicates that the Ararat VR start up sequence is completed. This
signal will transition to a logic low for power off sequencing and/or any Ararat VR
fault condition.
VSS
I
VSS is the ground plane for the processor.
VSSCACHESENSE
See VCCCACHESENSE
VSSCORESENSE
See VCCCORESENSE
VSSUNCORESENSE
See VCCUNCORESENSE
XDPOCPD[7:0]
I/O
Bidirectional XDP data
XDPOCP_STRB_IN_N
I
input clock center-aligned with XDPOCP_FRAME_N and XDPOCPD[7:0]
XDPOCP_STRB_OUT_N
O
output clock edge-aligned with XDPOCP_FRAME_N and XDPOCPD[7:0]
XDPOCP_FRAME_N
I/O
Bidirectional signal indicating valid data on XDPOCPD[7:0]
Table 7-1.
Signal Definitions Intel Itanium Processor 9300 Series
(Sheet 8 of 8)
Name
Type
Description