Техническая Спецификация для Intel LF80550KG0804M

Dual-Core Intel® Xeon® Processor 7100 Series Datasheet

67

BR0#
BR[3:1]#

I/O

I

BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The 

BREQ[3:0]# signals are interconnected in a rotating manner to individual 

processor pins. The tables below give the rotating interconnect between the 

processor and bus signals for 3-load configurations.

During power-on configuration, the central agent must assert the BR0# bus 

signal. All symmetric agents sample their BR[3:0]# pins on the active-to-

inactive transition of RESET#. The pin which the agent samples asserted 

determines its agent ID.

BSEL[1:0]

O

These output signals are used to select the front side bus frequency. The 

frequency is determined by the processor(s), chipset, and frequency 

synthesizer capabilities. All front side bus agents must operate at the same 

frequency. Individual processors will only operate at their specified front side 

bus frequency. See the appropriate platform design guide for implementation 

examples.
See 

 for output values. Refer to the appropriate platform design guide 

for termination recommendations.

COMP0

I

COMP0 must be terminated to V

SS

 on the baseboard using precision resistors. 

This input configures the AGTL+ drivers of the processor. Refer to the 

appropriate platform design guide and 

 for implementation details. 

CVID[3:0]

O

CVID[3:0] (Cache Voltage ID) pins are used to support automatic selection of 

V

CACHE

. These are open drain signals that are driven by the processor and must 

be pulled to no more than 3.3 V (+5% tolerance) with a resistor. Conversely, 

the V

CACHE

 VR output must be disabled prior to the voltage supply for these 

pins becoming invalid. The CVID pins are needed to support processor voltage 

specification variations. See 

 

for definitions of these pins. The V

CACHE

 

VR must supply the voltage that is requested by these pins, or disable itself.

D[63:0]#

I/O

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path 

between the processor front side bus agents, and must connect the 

appropriate pins on all such agents. The data driver asserts DRDY# to indicate 

a valid data transfer.
D[63:0]# are quad-pumped signals, and will thus be driven four times in a 

common clock period. D[63:0]# are latched off the falling edge of both 

DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to 

a pair of one DSTBP# and one DSTBN#. The following table shows the 

grouping of data signals to strobes and DBI#.
Furthermore, the DBI# pins determine the polarity of the data signals. Each 

group of 16 data signals corresponds to one DBI# signal. When the DBI# 

signal is active, the corresponding data group is inverted and therefore 

sampled active high. 

DBI[3:0]#

I/O

DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# 

and DEP[7:0]# signals. The DBI[3:0]# signals are activated when the data on 

the data bus is inverted. If more than half the data bits, within an 18-bit group 

(including ECC bits), would have been asserted electrically low, the bus agent 

may invert the data bus and corresponding ECC signals for that particular sub-

phase for that 18-bit group.

DBSY#

I/O

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data 

on the processor front side bus to indicate that the data bus is in use. The data 

bus is released after DBSY# is deasserted. This signal must connect the 

appropriate pins on all processor front side bus agents.

DEFER#

I

DEFER# is asserted by an agent to indicate that a transaction cannot be 

guaranteed in-order completion. Assertion of DEFER# is normally the 

responsibility of the addressed memory or I/O agent. This signal must connect 

the appropriate pins of all processor front side bus agents.

BREQ0#

BR0#

BR1#

BREQ1#

BR1#

BR0#

BREQ2#

BR2#

BR3#

BREQ3#

BR3#

BR2#