Руководство По Установке для Cisco Cisco D9858 Advanced Receiver Transcoder
Front Panel LEDs
78-4023074-01 Rev J
247
Alarm
Message
Type
Type
Message
Cause/Remedy
Description
Severity
LEC Timeout
Set
LEC Table
Missing/timeout
:channels
currently
unavailable
Missing/timeout
:channels
currently
unavailable
Cause: Possible
LEC Server or
Uplink issue.
LEC Server or
Uplink issue.
Remedy: If using
RF input, contact
the content
provider. If using
ASI output, ensure
the source has not
been changed for
the content
provider. Clear
alarm and notify
customer service if
the problem
persists.
RF input, contact
the content
provider. If using
ASI output, ensure
the source has not
been changed for
the content
provider. Clear
alarm and notify
customer service if
the problem
persists.
ECT Table is
not received in
the GDS
stream.
not received in
the GDS
stream.
LEC Timeout
Clear
LEC received
FPGA status
Set
FPGA Init failed
to go high
to go high
Cause: Hardware
issue.
issue.
Remedy: Clear
alarms, reset the
unit, notify
customer service if
the problem
persists.
alarms, reset the
unit, notify
customer service if
the problem
persists.
FPGA setup
failure or the
FPGA binary
identity does
not match the
FPGA registers.
failure or the
FPGA binary
identity does
not match the
FPGA registers.
Major
FPGA status
Set
FPGA Init and
Done failed to go
low
Done failed to go
low
Cause: Hardware
issue.
issue.
Remedy: Clear
alarms, reset the
unit, notify
customer service if
the problem
persists.
alarms, reset the
unit, notify
customer service if
the problem
persists.
FPGA setup
failure or the
FPGA binary
identity does
not match the
FPGA registers.
failure or the
FPGA binary
identity does
not match the
FPGA registers.
Major
FPGA status
Set
FPGA Init went
LOW (CRC
error)
LOW (CRC
error)
Cause: Hardware
issue.
issue.
Remedy: Clear
alarms, reset the
unit, notify
customer service if
the problem
persists.
alarms, reset the
unit, notify
customer service if
the problem
persists.
FPGA setup
failure or the
FPGA binary
identity does
not match the
FPGA registers.
failure or the
FPGA binary
identity does
not match the
FPGA registers.
Major