Справочник Пользователя для Aopen ax4pergn
80
A
A
X
X
4
4
P
P
E
E
R
R
-
-
G
G
/
/
A
A
X
X
4
4
P
P
E
E
R
R
-
-
G
G
N
N
O
O
n
n
l
l
i
i
n
n
e
e
M
M
a
a
n
n
u
u
a
a
l
l
C
C
N
N
R
R
(
(
C
C
o
o
m
m
m
m
u
u
n
n
i
i
c
c
a
a
t
t
i
i
o
o
n
n
a
a
n
n
d
d
N
N
e
e
t
t
w
w
o
o
r
r
k
k
i
i
n
n
g
g
R
R
i
i
s
s
e
e
r
r
)
)
The CNR specification provides the PC industry the opportunity to deliver a flexible and cost reduced method of implementing
LAN, home networking, DSL, USB, wireless, audio and modem subsystems widely used in today's "connected PCs". The CNR
specification is an open industry specification and is supported by OEMs, IHV card manufacturers, silicon supplier and
Microsoft.
LAN, home networking, DSL, USB, wireless, audio and modem subsystems widely used in today's "connected PCs". The CNR
specification is an open industry specification and is supported by OEMs, IHV card manufacturers, silicon supplier and
Microsoft.
D
D
D
D
R
R
(
(
D
D
o
o
u
u
b
b
l
l
e
e
D
D
a
a
t
t
a
a
R
R
a
a
t
t
e
e
)
)
R
R
A
A
M
M
DDR RAM utilizes the existing
(For ex, PC-100, PC-133) infrastructure and technology while doubling the nominal
bandwidth available to systems in an easy to design and simple to adopt way. Based on FSB frequency, DDR RAM on the
market are DDR200, DDR266 and DDR333 with more coming around soon.
DDR200, transfer bandwidth up to 200x64/8=1600MB/s (PC1600)
DDR266, transfer bandwidth up to 266x64/8=2100MB/s (PC2100)
DDR333, transfer bandwidth up to 333x64/8=2700MB/s (PC2700)
DDR400, transfer bandwidth up to 400x64/8=3200MB/s (PC3200)
market are DDR200, DDR266 and DDR333 with more coming around soon.
DDR200, transfer bandwidth up to 200x64/8=1600MB/s (PC1600)
DDR266, transfer bandwidth up to 266x64/8=2100MB/s (PC2100)
DDR333, transfer bandwidth up to 333x64/8=2700MB/s (PC2700)
DDR400, transfer bandwidth up to 400x64/8=3200MB/s (PC3200)
E
E
C
C
C
C
(
(
E
E
r
r
r
r
o
o
r
r
C
C
h
h
e
e
c
c
k
k
i
i
n
n
g
g
a
a
n
n
d
d
C
C
o
o
r
r
r
r
e
e
c
c
t
t
i
i
o
o
n
n
)
)
The ECC mode needs 8 ECC bits for 64-bit data. Each time memory is accessed; ECC bits are updated and checked by a
special algorithm. The ECC algorithm has the ability to detect double-bit error and automatically correct single-bit error while
parity mode can only detect single-bit error.
special algorithm. The ECC algorithm has the ability to detect double-bit error and automatically correct single-bit error while
parity mode can only detect single-bit error.
E
E
E
E
P
P
R
R
O
O
M
M
(
(
E
E
l
l
e
e
c
c
t
t
r
r
o
o
n
n
i
i
c
c
E
E
r
r
a
a
s
s
a
a
b
b
l
l
e
e
P
P
r
r
o
o
g
g
r
r
a
a
m
m
m
m
a
a
b
b
l
l
e
e
R
R
O
O
M
M
)
)
Also known as E
2
PROM. Both EEPROM and
can be re-programmed by electronic signals, but the interface
technology is different. Size of EEPROM is much smaller than flash ROM.