Справочник Пользователя для Nxp Semiconductors TFA9812
TFA9812_2
© NXP B.V. 2009. All rights reserved.
Preliminary data sheet
Rev. 02 — 22 January 2009
32 of 66
NXP Semiconductors
TFA9812
BTL stereo Class-D audio amplifier with I
2
S input
9.5.3 Digital input format
9.5.4 Equalizer configuration
Table 31.
Bit description of register 00h: miscellaneous I
2
C interpolator settings
Bit
Symbol
Description
15 to 8
VOL_L[15:8]
See
for suppression levels on left channel as
function of data byte setting.
7 to 0
VOL_R[7:0]
See
for suppression levels on right channel as
function of data byte setting.
Table 32.
Register address 02h: digital input format
Bit
15
14
13
12
11
10
9
8
Symbol
RSD
RSD
RSD
RSD
RSD
RSD
RSD
RSD
Default
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Symbol
RSD
RSD
RSD
RSD
DI_FOR2
DI_FOR1
DI_FOR0
WS_POL
Default
0
0
0
0
0
1
1
0
Table 33.
Bit description of register 02h: digital input format
Bit
Symbol
Description
3 to 1
DI_FOR[2:0]
Digital audio input format:
0 = RSD
1 = RSD
2 = MSB-justified data up to 24 bits
3 = I
2
S data up to 24 bits
4 = LSB-justified 16-bit data
5 = LSB-justified 18-bit data
6 = LSB-justified 20-bit data
7 = LSB-justified 24-bit data
0
WS_POL
Enable WS signal polarity inversion:
0 = No WS signal polarity inversion
1 = WS signal polarity inversion enabled
Table 34.
Register address 03h: equalizer configuration
Bit
15
14
13
12
11
10
9
8
Symbol
RSD
RSD
RSD
RSD
RSD
RSD
RSD
RSD
Default
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Symbol
RSD
RSD
RSD
RSD
RSD
RSD
EQ_BP
EQ_BND
Default
0
0
0
0
0
0
1
0