Справочник Пользователя для Nxp Semiconductors TFA9812

TFA9812_2

© NXP B.V. 2009. All rights reserved.

[1]

R

s

 is the series resistance of inductor of low-pass LC filter in the application.

[2]

Output power measured across the loudspeaker load. This is based on indirect measurement of R

DSon

.

t

PD

propagation delay

f

s

 =

8 kHz

-

3.6

-

ms

11.025 kHz

-

2.58

-

ms

12 kHz

-

2.39

-

ms

16 kHz

-

1.78

-

ms

22.05 kHz

-

1.3

-

ms

24 kHz

-

1.18

-

ms

32 kHz

-

892

-

µ

s

44.1 kHz

-

664

-

µ

s

48 kHz

-

600

-

µ

s

64 kHz

-

458

-

µ

s

88.2 kHz

-

320

-

µ

s

96 kHz

-

306

-

µ

s

128 kHz

-

67.2

-

µ

s

176.4 kHz

-

48

-

µ

s

192 kHz

-

40.8

-

µ

s

t

r

rise time

I

O

 = 0 A

-

10

-

ns

t

f

fall time

I

O

 = 0 A

-

10

-

ns

t

w(min)

minimum pulse width

I

O

 = 0 A

-

40

-

ns

R

DSon

drain-source on-state resistance

per output MOSFET, for low and high
side

-

0.28

0.35

Ω

δ

max

maximum duty factor

-

-

0.96

-

 …continued

Unless specified otherwise, V

DDA

= V

DDP

= 12 V, V

DDA(3V3)

= V

DDD(3V3)

= 3.3 V, T

amb

= 25

°

C, R

s

 < 0.1

Ω

[1]

, R

L

= 8

Ω

,

f

i

= 1 kHz, f

s

= 44.1 kHz, f

sw

= 400 kHz, 24-bit I

2

S input data, MCLK clock mode, typical application diagram (

Figure 13

).

V

DDD(3V3)

= V

DDA(3V3)

= 2.7 V to 3.6 V; V

DDA

= V

DDP

= 8 V to 20 V;T

amb

=

−

20

°

C to +85

°

C; all voltages referenced to ground;

unless otherwise specified.

f

SCL

SCL clock frequency

-

-

400

kHz

t

LOW

LOW period of the SCL clock

1.3

-

-

µ

s

t

HIGH

HIGH period of the SCL clock

0.6

-

-

µ

s

t

r

rise time

SDA and SCL signals

20 + 0.1 C

b

-

-

ns

t

f

fall time

SDA and SCL signals

20 + 0.1 C

b

-

-

ns

t

HD;STA

hold time (repeated) START
condition

0.6

-

-

µ

s

t

SU;STA

set-up time for a repeated START
condition

0.6

-

-

µ

s