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Refer to the 

 section for more information on 

the synchronization clock.

The PFI synchronization clock is the same for all routing operations in which 

PFI <0..5> is defined as the output, although the divide-down ratio for this clock (full rate, 
first divider, second divider) may be chosen on a per route basis.

The PXI triggers go to all the slots in the chassis. All modules receive the 
same PXI triggers, so PXI trigger 0 is the same for Slot 2 as it is for Slot 3, 
and so on. This feature makes the PXI triggers convenient in situations 
where you want, for instance, to start an acquisition on several devices at 
the same time because all modules will receive the same trigger.

The frequency on the PXI triggers should not exceed 20 MHz to preserve 
signal integrity. The signals do not reach each slot at precisely the same 
time. A difference of several nanoseconds between slots can occur in an 
eight-slot chassis. However, this delay is not a problem for many 
applications. You can route signals to the PXI triggers from PFI <0..5>, 
from the PXI star triggers, or from other PXI triggers. You also can route 
PXI_CLK10 or the DDS clock to a PXI trigger line (PXI_TRIG <0..7>) 
using the synchronization clock.

You can independently select the output signal source for each PXI trigger 
line from one of the following sources:

•

PFI <0..5>

•

Another PXI trigger <0..7> (PXI_TRIG <0..7>)

•

PXI_STAR <0..16>

•

Global software trigger

•

PXI_Trig/PXI_Star synchronization clock

The PXI_Trig/PXI_Star synchronization clock may be any of the following 
signals:

•

DDS clock

•

PXI_CLK10

•

PFI 0 Input

•

Any of the previously listed signals divided by the first frequency 
divider (2

, up to 512)

•

Any of the previously listed signals divided by the second frequency 
divider (2

, up to 512)