Техническая Спецификация для Intel Xeon Dual-Core 5050 HH80555KF0804M

Dual-Core Intel® Xeon® Processor 5000 Series Datasheet

67

TESTHI[11:0]

I

TESTHI[11:0] must be connected to a V

TT

 power source through a resistor for proper 

processor operation. Refer to 

 for TESTHI grouping restrictions.

THERMDA
THERMDA2

Other

Thermal Diode Anode. THERMDA connects to processor core 0, THERMDA2 connects 

to processor core 1. Refer to the appropriate platform design guidelines for 

implementation details.

THERMDC
THERMDC2

Other

Thermal Diode Cathode. THERMDC connects to processor core 0. THERMDC2 

connects to processor core 1. Refer to the appropriate platform design guidelines for 

implementation details.

THERMTRIP#

O

Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction 

temperature has reached a temperature beyond which permanent silicon damage 

may occur. Measurement of the temperature is accomplished through an internal 

thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its 

internal clocks (thus halting program execution) in an attempt to reduce the 

processor junction temperature. To protect the processor its core voltage (V

CC

) must 

be removed following the assertion of THERMTRIP#. Intel is currently evaluating 

whether V

TT

 must also be removed.

Driving of the THERMTRIP# signals is enabled within 10 ms of the assertion of 

PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated, 

THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-assertion 

of the PWRGOOD signal will de-assert THERMTRIP#, if the processor’s junction 

temperature remains at or above the trip level, THERMTRIP# will again be asserted 

within 10 ms of the assertion of PWRGOOD.

1

TMS

I

TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
See the eXtended Debug Port: Debug Port Design Guide for UP and DP Platforms for 

further information.

TRDY#

I

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive 

a write or implicit writeback data transfer. TRDY# must connect the appropriate pins 

of all FSB agents.

TRST#

I

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven 

low during power on Reset.

V

CCA

I

V

CCA

 provides isolated power for the analog portion of the internal processor core 

PLL’s. Refer to the appropriate platform design guidelines for complete 

implementation details.

V

CCIOPLL

I

V

CCIOPLL

 provides isolated power for digital portion of the internal processor core 

PLL’s. Follow the guidelines for V

CCA

, and refer to the appropriate platform design 

guidelines for complete implementation details.

VCC_DIE_SENSE
VCC_DIE_SENSE2

O

VCC_DIE_SENSE and VCC_DIE_SENSE2 provide an isolated, low impedance 

connection to each processor core power and ground. These signals should be 

connected to the voltage regulator feedback signal, which insures the output voltage 

(that is, processor voltage) remains within specification. Please see the applicable 

platform design guide for implementation details.

VID[5:0]

O

VID[5:0] (Voltage ID) pins are used to support automatic selection of power supply 

voltages (V

CC

). These are CMOS signals that are driven by the processor and must be 

pulled up through a resistor. Conversely, the voltage regulator output must be 

disabled prior to the voltage supply for these pins becomes invalid. The VID pins are 

needed to support processor voltage specification variations. See 

 for 

definitions of these pins. The VR must supply the voltage that is requested by these 

pins, or disable itself.

VID_SELECT

O

VID_SELECT is an output from the processor which selects the appropriate VID table 

for the Voltage Regulator. Dual-Core Intel Xeon Processor 5000 series pull this signal 

to ground on the package as this signal is not connected to the processor die.

VSS_DIE_SENSE
VSS_DIE_SENSE2

O

VSS_DIE_SENSE and VSS_DIE_SENSE2 provide an isolated, low impedance 

connection to each processor core power and ground. These signals should be 

connected to the voltage regulator feedback signal, which insures the output voltage 

(that is, processor voltage) remains within specification. Please see the applicable 

platform design guide for implementation details.

V

SSA

I

V

SSA

 provides an isolated, internal ground for internal PLL’s. Do not connect directly 

to ground. This pin is to be connected to V

CCA

 and V

CCIOPLL

 through a discrete filter 

circuit.