Справочник Пользователя для IBM powerpc 750gx
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
gx_02.fm.(1.2)
March 27, 2006
March 27, 2006
Programming Model
Page 57 of 377
2. Programming Model
This chapter describes the 750GX programming model, emphasizing those features specific to the 750GX
processor and summarizing those that are common to PowerPC processors. It consists of three major
sections, which describe the following topics.
processor and summarizing those that are common to PowerPC processors. It consists of three major
sections, which describe the following topics.
• Registers implemented in the 750GX
• Operand conventions
• 750GX instruction set
• Operand conventions
• 750GX instruction set
For detailed information about architecture-defined features, see the PowerPC Microprocessor Family: The
Programming Environments Manual.
Programming Environments Manual.
2.1 PowerPC 750GX Processor Register Set
This section describes the registers implemented in the 750GX. It includes an overview of registers defined
by the PowerPC Architecture, highlighting differences in how these registers are implemented in the 750GX,
and a detailed description of 750GX-specific registers. Full descriptions of the architecture-defined register
set are provided in Chapter 2, “PowerPC Register Set” in the PowerPC Microprocessor Family: The Program-
ming Environments Manual.
by the PowerPC Architecture, highlighting differences in how these registers are implemented in the 750GX,
and a detailed description of 750GX-specific registers. Full descriptions of the architecture-defined register
set are provided in Chapter 2, “PowerPC Register Set” in the PowerPC Microprocessor Family: The Program-
ming Environments Manual.
Registers are defined at all three levels of the PowerPC Architecture—user instruction set architecture
(UISA), virtual environment architecture (VEA), and operating environment architecture (OEA). The PowerPC
Architecture defines register-to-register operations for all computational instructions. Source data for these
instructions are accessed from the on-chip registers or are provided as immediate values embedded in the
opcode. The 3-register instruction format allows specification of a target register distinct from the two source
registers, thus preserving the original data for use by other instructions and reducing the number of instruc-
tions required for certain operations. Data is transferred between memory and registers with explicit load-and-
store instructions only.
(UISA), virtual environment architecture (VEA), and operating environment architecture (OEA). The PowerPC
Architecture defines register-to-register operations for all computational instructions. Source data for these
instructions are accessed from the on-chip registers or are provided as immediate values embedded in the
opcode. The 3-register instruction format allows specification of a target register distinct from the two source
registers, thus preserving the original data for use by other instructions and reducing the number of instruc-
tions required for certain operations. Data is transferred between memory and registers with explicit load-and-
store instructions only.
2.1.1 Register Set
The registers implemented on the 750GX are shown in Figure 2-1 on page 58. The number to the right of the
special-purpose registers (SPRs) indicates the number that is used in the syntax of the instruction operands
to access the register (for example, the number used to access the Integer Exception Register (XER) is
SPR 1). These registers can be accessed using the Move-to Special Purpose Register (mtspr) and Move-
from Special Purpose Register (mfspr) instructions.
special-purpose registers (SPRs) indicates the number that is used in the syntax of the instruction operands
to access the register (for example, the number used to access the Integer Exception Register (XER) is
SPR 1). These registers can be accessed using the Move-to Special Purpose Register (mtspr) and Move-
from Special Purpose Register (mfspr) instructions.