Справочник Пользователя для Intel CM8064601466203
Specification Update
9
Errata (Sheet 1 of 5)
Number
Steppings
Status
ERRATA
C-0
HSD1
X
No Fix
LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode
HSD2
X
No Fix
EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change
HSD3
X
No Fix
MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error
HSD4
X
No Fix
LER MSRs May Be Unreliable
HSD5
X
No Fix
MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
HSD6
X
No Fix
An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a System Hang
HSD7
X
No Fix
#GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error Code
HSD8
X
No Fix
FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM
HSD9
X
No Fix
APIC Error “Received Illegal Vector” May be Lost
HSD10
X
No Fix
Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering Violations
HSD11
X
No Fix
Performance Monitor Precise Instruction Retired Event May Present Wrong Indications
HSD12
X
No Fix
CR0.CD Is Ignored in VMX Operation
HSD13
X
No Fix
Instruction Fetch May Cause Machine Check if Page Size and Memory Type Was Changed Without Invalidation
HSD14
X
No Fix
Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX.vvvv May Produce a #NM Exception
HSD15
X
No Fix
Processor May Fail to Acknowledge a TLP Request
HSD16
X
No Fix
Interrupt From Local APIC Timer May Not Be Detectable While Being Delivered
HSD17
X
No Fix
PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be Incorrect
HSD18
X
No Fix
PCIe* Controller May Incorrectly Log Errors on Transition to RxL0s
HSD19
X
No Fix
Unused PCIe* Lanes May Report Correctable Errors
HSD20
X
No Fix
Accessing Physical Memory Space 0-640K through the Graphics Aperture May Cause Unpredictable System Behavior
HSD21
X
No Fix
PCIe Root Port May Not Initiate Link Speed Change
HSD22
X
No Fix
Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected
HSD23
X
No Fix
DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is Followed by a Store or an MMX Instruction
HSD24
X
No Fix
VEX.L is Not Ignored with VCVT*2SI Instructions
HSD25
X
No Fix
Certain Local Memory Read / Load Retired PerfMon Events May Undercount